Simulation Results: csrng

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.39 %
  • code
  • 92.34 %
  • assert
  • 94.32 %
  • func
  • 75.50 %
  • block
  • 97.05 %
  • line
  • 97.73 %
  • branch
  • 92.68 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 30.004us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 22.086us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 3.000s 18.678us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 25.000s 1147.841us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 6.000s 99.765us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 68.691us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 3.000s 18.678us 1 1 100.00
csrng_csr_aliasing 6.000s 99.765us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 277.936us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 56.000s 1986.378us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 56.000s 1986.378us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 149.000s 3128.614us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 37.045us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 4.000s 37.700us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 7.000s 155.326us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 7.000s 155.326us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 22.086us 1 1 100.00
csrng_csr_rw 3.000s 18.678us 1 1 100.00
csrng_csr_aliasing 6.000s 99.765us 1 1 100.00
csrng_same_csr_outstanding 4.000s 97.249us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 22.086us 1 1 100.00
csrng_csr_rw 3.000s 18.678us 1 1 100.00
csrng_csr_aliasing 6.000s 99.765us 1 1 100.00
csrng_same_csr_outstanding 4.000s 97.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
csrng_tl_intg_err 8.000s 175.220us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 2.000s 2.857us 0 1 0.00
csrng_csr_rw 3.000s 18.678us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 277.936us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 149.000s 3128.614us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 277.936us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 149.000s 3128.614us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 277.936us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 8.000s 175.220us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
csrng_sec_cm 4.000s 151.144us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 69.957us 1 1 100.00
csrng_err 3.000s 19.768us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 7.000s 88.753us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 81431481118284753920561691530081078829070022227899981265336704748722293036902 99
UVM_INFO @ 2856930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 29789759726694317529665952760807561700976943225800611632713169449032891706508 116
UVM_INFO @ 88753243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---