Simulation Results: dma

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.08 %
  • code
  • 91.85 %
  • assert
  • 96.29 %
  • func
  • 61.09 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 83.12 %
  • FSM
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 343.911us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 6.000s 291.953us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 583.546us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 23.119us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 1.000s 71.376us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 12.000s 4201.829us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 7.000s 1188.588us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 3.000s 116.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 1.000s 71.376us 1 1 100.00
dma_csr_aliasing 7.000s 1188.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 44.000s 4754.156us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 660.000s 41634.791us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 298.000s 71920.229us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 298.000s 71920.229us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 660.000s 41634.791us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 112.000s 16356.446us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 298.000s 71920.229us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 8.000s 1126.300us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 167.000s 11187.103us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 2.000s 18.950us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 13.226us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 2.000s 210.714us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 2.000s 210.714us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 23.119us 1 1 100.00
dma_csr_rw 1.000s 71.376us 1 1 100.00
dma_csr_aliasing 7.000s 1188.588us 1 1 100.00
dma_same_csr_outstanding 3.000s 77.934us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 23.119us 1 1 100.00
dma_csr_rw 1.000s 71.376us 1 1 100.00
dma_csr_aliasing 7.000s 1188.588us 1 1 100.00
dma_same_csr_outstanding 3.000s 77.934us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 231.992us 1 1 100.00
dma_generic_stress 112.000s 16356.446us 1 1 100.00
dma_handshake_stress 298.000s 71920.229us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 1352.188us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 2.000s 182.242us 1 1 100.00
dma_sec_cm 2.000s 13.594us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 108.000s 113800.440us 1 1 100.00
dma_longer_transfer 3.000s 384.071us 1 1 100.00
dma_stress_all_with_rand_reset 11.000s 4640.468us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 83130967612983291522987663487980805902268712456082385259091929013351359567783 106
UVM_INFO @ 4640467663ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---