Simulation Results: edn/edn1

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.70 %
  • code
  • 84.82 %
  • assert
  • 98.44 %
  • func
  • 79.83 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 90.23 %
  • toggle
  • 95.83 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.130s 46.876us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.140s 190.263us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.160s 46.649us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 6.960s 277.841us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.590s 144.497us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 2.460s 115.351us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.160s 46.649us 1 1 100.00
edn_csr_aliasing 1.590s 144.497us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.700s 221.860us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.700s 221.860us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.700s 221.860us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.200s 24.586us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.280s 24.360us 1 1 100.00
errs 1 1 100.00
edn_err 1.350s 46.287us 1 1 100.00
disable 2 2 100.00
edn_disable 1.110s 38.380us 1 1 100.00
edn_disable_auto_req_mode 1.340s 35.084us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.420s 93.764us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.090s 20.643us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.220s 100.930us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.880s 160.089us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.880s 160.089us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.140s 190.263us 1 1 100.00
edn_csr_rw 1.160s 46.649us 1 1 100.00
edn_csr_aliasing 1.590s 144.497us 1 1 100.00
edn_same_csr_outstanding 1.650s 31.641us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.140s 190.263us 1 1 100.00
edn_csr_rw 1.160s 46.649us 1 1 100.00
edn_csr_aliasing 1.590s 144.497us 1 1 100.00
edn_same_csr_outstanding 1.650s 31.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.550s 193.962us 1 1 100.00
edn_tl_intg_err 2.490s 442.039us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.300s 16.927us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.280s 24.360us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.550s 193.962us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.550s 193.962us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.550s 193.962us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.550s 193.962us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.280s 24.360us 1 1 100.00
edn_sec_cm 3.550s 193.962us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.280s 24.360us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.490s 442.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 110.430s 8759.587us 1 1 100.00