Simulation Results: entropy_src/rng_16bits

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.60 %
  • code
  • 82.06 %
  • assert
  • 74.20 %
  • func
  • 49.55 %
  • block
  • 94.08 %
  • line
  • 97.73 %
  • branch
  • 86.00 %
  • toggle
  • 52.85 %
  • FSM
  • 91.67 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 4.000s 69.902us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 3.000s 73.514us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 3.000s 22.222us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 28.000s 977.733us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 4.000s 37.823us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 3.000s 20.112us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 3.000s 22.222us 1 1 100.00
entropy_src_csr_aliasing 4.000s 37.823us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 4.000s 69.902us 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
entropy_src_fw_ov 3602.085s 0.000us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 3602.085s 0.000us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 324.000s 13073.036us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
entropy_src_intr 34.000s 4451.099us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
entropy_src_functional_alerts 6.000s 180.664us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 117.000s 13535.441us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 42.298us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 68.000s 2502.025us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 3.000s 33.954us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 16.256us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 7.000s 1799.218us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 7.000s 1799.218us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 73.514us 1 1 100.00
entropy_src_csr_rw 3.000s 22.222us 1 1 100.00
entropy_src_csr_aliasing 4.000s 37.823us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 23.366us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 3.000s 73.514us 1 1 100.00
entropy_src_csr_rw 3.000s 22.222us 1 1 100.00
entropy_src_csr_aliasing 4.000s 37.823us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 23.366us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 4.000s 151.607us 1 1 100.00
entropy_src_tl_intg_err 4.000s 250.008us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
entropy_src_cfg_regwen 3.000s 73.074us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
entropy_src_fw_ov 3602.085s 0.000us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 42.298us 1 1 100.00
entropy_src_sec_cm 4.000s 151.607us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 42.298us 1 1 100.00
entropy_src_sec_cm 4.000s 151.607us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 419.000s 14036.705us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 42.298us 1 1 100.00
entropy_src_sec_cm 4.000s 151.607us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 42.298us 1 1 100.00
entropy_src_sec_cm 4.000s 151.607us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 42.298us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 6.000s 180.664us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 4.000s 250.008us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 189.000s 13092.890us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 10.000s 345.284us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_hi_threshold 1 test run
entropy_src_stress_all_with_rand_reset 37246776207957474033871683819748870396453160486059302877867914822534183210237 420
UVM_INFO @ 345283686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
entropy_src_fw_ov 108175639003572834532010958556205155289819421274347187821631085601195099201625 None
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 107508255645634591960599890082058617195408656165699134935358675592658580058954 113
UVM_INFO @ 20112209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---