Simulation Results: hmac

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.81 %
  • code
  • 83.19 %
  • assert
  • 97.17 %
  • func
  • 29.06 %
  • block
  • 97.46 %
  • line
  • 98.39 %
  • branch
  • 93.64 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.000s 859.348us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 113.422us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 21.340us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 384.954us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 7.000s 1685.260us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 2.000s 126.492us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 21.340us 1 1 100.00
hmac_csr_aliasing 7.000s 1685.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 107.000s 2588.176us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 100.000s 7737.662us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 328.000s 9609.461us 1 1 100.00
hmac_test_sha384_vectors 558.000s 16618.739us 1 1 100.00
hmac_test_sha512_vectors 540.000s 176780.895us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 263.663us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 1237.891us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 740.431us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 23.000s 2037.581us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 325.000s 7681.535us 1 1 100.00
error 1 1 100.00
hmac_error 102.000s 1982.493us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 63.000s 53074.470us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.000s 859.348us 1 1 100.00
hmac_long_msg 107.000s 2588.176us 1 1 100.00
hmac_back_pressure 100.000s 7737.662us 1 1 100.00
hmac_datapath_stress 325.000s 7681.535us 1 1 100.00
hmac_burst_wr 23.000s 2037.581us 1 1 100.00
hmac_stress_all 751.000s 181492.499us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.000s 859.348us 1 1 100.00
hmac_long_msg 107.000s 2588.176us 1 1 100.00
hmac_back_pressure 100.000s 7737.662us 1 1 100.00
hmac_datapath_stress 325.000s 7681.535us 1 1 100.00
hmac_wipe_secret 63.000s 53074.470us 1 1 100.00
hmac_test_sha256_vectors 328.000s 9609.461us 1 1 100.00
hmac_test_sha384_vectors 558.000s 16618.739us 1 1 100.00
hmac_test_sha512_vectors 540.000s 176780.895us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 263.663us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 1237.891us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 740.431us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.000s 859.348us 1 1 100.00
hmac_long_msg 107.000s 2588.176us 1 1 100.00
hmac_back_pressure 100.000s 7737.662us 1 1 100.00
hmac_datapath_stress 325.000s 7681.535us 1 1 100.00
hmac_burst_wr 23.000s 2037.581us 1 1 100.00
hmac_error 102.000s 1982.493us 1 1 100.00
hmac_wipe_secret 63.000s 53074.470us 1 1 100.00
hmac_test_sha256_vectors 328.000s 9609.461us 1 1 100.00
hmac_test_sha384_vectors 558.000s 16618.739us 1 1 100.00
hmac_test_sha512_vectors 540.000s 176780.895us 1 1 100.00
hmac_test_hmac256_vectors 10.000s 263.663us 1 1 100.00
hmac_test_hmac384_vectors 15.000s 1237.891us 1 1 100.00
hmac_test_hmac512_vectors 15.000s 740.431us 1 1 100.00
hmac_stress_all 751.000s 181492.499us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 751.000s 181492.499us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 17.817us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 19.140us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.000s 50.175us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.000s 50.175us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 113.422us 1 1 100.00
hmac_csr_rw 2.000s 21.340us 1 1 100.00
hmac_csr_aliasing 7.000s 1685.260us 1 1 100.00
hmac_same_csr_outstanding 3.000s 53.569us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 113.422us 1 1 100.00
hmac_csr_rw 2.000s 21.340us 1 1 100.00
hmac_csr_aliasing 7.000s 1685.260us 1 1 100.00
hmac_same_csr_outstanding 3.000s 53.569us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 247.694us 1 1 100.00
hmac_tl_intg_err 3.000s 51.708us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.000s 51.708us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.000s 859.348us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.000s 75.363us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 43.000s 19309.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 33.508us 1 1 100.00