Simulation Results: i2c

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.15 %
  • code
  • 89.14 %
  • assert
  • 97.25 %
  • func
  • 81.05 %
  • block
  • 95.92 %
  • line
  • 95.34 %
  • branch
  • 92.68 %
  • toggle
  • 86.53 %
  • FSM
  • 82.01 %
Validation stages
V1
100.00%
V2
82.93%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 196.000s 12303.375us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 12.000s 7062.377us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 1.000s 19.259us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 2.000s 16.840us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 6.000s 1374.788us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 3.000s 113.561us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 2.000s 27.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 2.000s 16.840us 1 1 100.00
i2c_csr_aliasing 3.000s 113.561us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 2.000s 30.036us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 3600.000s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 339.000s 24482.480us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 2.000s 78.323us 1 1 100.00
host_fifo_watermark 0 1 0.00
i2c_host_fifo_watermark 3600.000s 0.000us 0 1 0.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 1769.000s 7698.570us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 3.000s 390.828us 1 1 100.00
i2c_host_fifo_fmt_empty 31.000s 732.705us 1 1 100.00
i2c_host_fifo_reset_rx 6.000s 735.795us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 731.000s 2074.067us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 17.000s 628.269us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 3.000s 463.795us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 6.000s 1238.094us 0 1 0.00
target_stress_all 0 1 0.00
i2c_target_stress_all 3600.000s 0.000us 0 1 0.00
target_maxperf 1 1 100.00
i2c_target_perf 5.000s 1216.848us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 32.000s 6487.250us 1 1 100.00
i2c_target_intr_smoke 5.000s 2792.012us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 3.000s 206.265us 1 1 100.00
i2c_target_fifo_reset_tx 2.000s 231.415us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 8.000s 8381.280us 1 1 100.00
i2c_target_stress_rd 32.000s 6487.250us 1 1 100.00
i2c_target_intr_stress_wr 201.000s 9618.023us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 10.000s 999.656us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 933.000s 2598.417us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 8.000s 1245.383us 1 1 100.00
target_mode_glitch 1 1 100.00
i2c_target_hrst 4.000s 349.033us 1 1 100.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 5.000s 1125.038us 1 1 100.00
i2c_target_fifo_watermarks_tx 2.000s 123.882us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 339.000s 24482.480us 1 1 100.00
i2c_host_perf_precise 4.000s 325.796us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 17.000s 628.269us 1 1 100.00
target_mode_tx_stretch_ctrl 0 1 0.00
i2c_target_tx_stretch_ctrl 3.000s 13.305us 0 1 0.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 4.000s 445.162us 1 1 100.00
i2c_target_nack_acqfull_addr 4.000s 2463.611us 1 1 100.00
i2c_target_nack_txstretch 4.000s 1366.101us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 9.000s 1939.364us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 4.000s 2518.407us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 2.000s 16.352us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 2.000s 15.246us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 9.000s 139.367us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 9.000s 139.367us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 1.000s 19.259us 1 1 100.00
i2c_csr_rw 2.000s 16.840us 1 1 100.00
i2c_csr_aliasing 3.000s 113.561us 1 1 100.00
i2c_same_csr_outstanding 2.000s 45.737us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 1.000s 19.259us 1 1 100.00
i2c_csr_rw 2.000s 16.840us 1 1 100.00
i2c_csr_aliasing 3.000s 113.561us 1 1 100.00
i2c_same_csr_outstanding 2.000s 45.737us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 3.000s 196.525us 1 1 100.00
i2c_sec_cm 2.000s 113.701us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 3.000s 196.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 8.000s 407.577us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 4.000s 131.818us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 11.000s 749.489us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
i2c_host_fifo_watermark 113611903867679478019989886970469431445559388584384112835430544190285884407748 None
i2c_host_stress_all 41013557572977756212891690539801499523374209961944444477819955347536889878672 None
i2c_target_stress_all 79339582157500418218776648795262092096216790955765490681795047247101215710872 None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between 2 test runs
i2c_host_error_intr 94132318981072722781767727785474701767291810297995924059326218494837464069773 97
UVM_INFO @ 30036154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 46199303907289589671201535764100249377126723681397682770341886553018437406431 101
UVM_INFO @ 749488675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between 1 test run
i2c_target_glitch 60439657525091879469577750496753460952561547722699644405541363468348807639721 93
UVM_INFO @ 1238094368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) 1 test run
i2c_target_unexp_stop 99828953114494735279146979697849874914592969369847251208763025467766001038370 87
UVM_INFO @ 131818196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
i2c_host_stress_all_with_rand_reset 45396897382805917164787088911410045687328159074511583802330502767280000149900 95
UVM_INFO @ 407577340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:714) [scoreboard] controller_mode_rd_obs_fifo item uncompared: 1 test run
i2c_host_mode_toggle 41540091319682114188778457046038471257545878152230610468849274355365188677567 94
----------------------------------------------------
Name Type Size Value
----------------------------------------------------
mon_dut_item i2c_item - @17295
UVM_FATAL (i2c_base_vseq.sv:882) [i2c_target_tx_stretch_ctrl_vseq] Check failed (std::randomize(transfer_lengths) with {transfer_lengths.size() == num_transfers; transfer_lengths.sum() == num_data_total; foreach (transfer_lengths[i]) { transfer_lengths[i] inside {[cfg.min_xfer_len : num_data_total]}; } transfer_lengths[*] > *; transfer_lengths[num_transfers - *] > *;}) Randomization failed! 1 test run
i2c_target_tx_stretch_ctrl 47206308156162843819544058876506732937463356537258970020431640286384899763735 109
UVM_INFO @ 13305385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---