Simulation Results: keymgr_dpe/darjeeling

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 55.66 %
  • code
  • 59.34 %
  • assert
  • 96.25 %
  • func
  • 11.38 %
  • block
  • 94.73 %
  • line
  • 95.20 %
  • branch
  • 83.74 %
  • toggle
  • 43.04 %
  • FSM
  • 15.38 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 1 0.00
keymgr_dpe_smoke 14.000s 786.362us 0 1 0.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 19.928us 1 1 100.00
csr_rw 1 1 100.00
keymgr_dpe_csr_rw 2.000s 18.956us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 13.000s 1790.701us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 6.000s 321.906us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 3.000s 90.212us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_dpe_csr_rw 2.000s 18.956us 1 1 100.00
keymgr_dpe_csr_aliasing 6.000s 321.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 1 1 100.00
keymgr_dpe_intr_test 2.000s 14.665us 1 1 100.00
alert_test 1 1 100.00
keymgr_dpe_alert_test 2.000s 12.383us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_dpe_tl_errors 4.000s 434.434us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_dpe_tl_errors 4.000s 434.434us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_dpe_csr_hw_reset 2.000s 19.928us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 18.956us 1 1 100.00
keymgr_dpe_csr_aliasing 6.000s 321.906us 1 1 100.00
keymgr_dpe_same_csr_outstanding 4.000s 82.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_dpe_csr_hw_reset 2.000s 19.928us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 18.956us 1 1 100.00
keymgr_dpe_csr_aliasing 6.000s 321.906us 1 1 100.00
keymgr_dpe_same_csr_outstanding 4.000s 82.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
keymgr_dpe_sec_cm 15.000s 884.848us 1 1 100.00
keymgr_dpe_tl_intg_err 5.000s 224.081us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 4.000s 173.639us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_dpe_shadow_reg_errors 4.000s 173.639us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_dpe_shadow_reg_errors 4.000s 173.639us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_dpe_shadow_reg_errors 4.000s 173.639us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 7.000s 152.730us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_dpe_sec_cm 15.000s 884.848us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_dpe_sec_cm 15.000s 884.848us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 1 test run
keymgr_dpe_smoke 61123242446990326332090693541202402868053683653837433134338639324568102061335 3567
UVM_INFO @ 786361537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---