Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.95 %
  • code
  • 91.45 %
  • assert
  • 96.69 %
  • func
  • 78.71 %
  • block
  • 96.16 %
  • line
  • 97.08 %
  • branch
  • 90.23 %
  • toggle
  • 83.27 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
73.33%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 3.000s 41.977us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 15.922us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 123.086us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 3.000s 181.587us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 86.180us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 19.320us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 123.086us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 86.180us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2128.823us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 3.000s 60.017us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
security_escalation 2 7 28.57
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 1202.132us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.000s 51.824us 0 1 0.00
lc_ctrl_jtag_errors 29.000s 5527.885us 1 1 100.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 4.000s 171.297us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 4.000s 51.824us 0 1 0.00
lc_ctrl_jtag_errors 29.000s 5527.885us 1 1 100.00
lc_ctrl_jtag_access 9.000s 1079.197us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.000s 841.468us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 5.000s 134.981us 1 1 100.00
lc_ctrl_jtag_csr_rw 4.000s 173.239us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 9.000s 3737.781us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.000s 1131.179us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 49.623us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 165.138us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 238.797us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 113.427us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 67.302us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.496s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 3.000s 23.044us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 37.271us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 37.271us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.922us 1 1 100.00
lc_ctrl_csr_rw 2.000s 123.086us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 86.180us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 73.318us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 15.922us 1 1 100.00
lc_ctrl_csr_rw 2.000s 123.086us 1 1 100.00
lc_ctrl_csr_aliasing 3.000s 86.180us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 73.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 85.210us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 85.210us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 2128.823us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 582.749us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 1202.132us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.000s 1242.423us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 529.816us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.000s 529.816us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 71558287003094025389105567186786113445071254718898739468599152999834082120097 None
lc_ctrl_state_post_trans 104085858124799728869946164986951893981930749422614740760705717906462808120876 None
lc_ctrl_prog_failure 110416483785185506872911344472599858400652243968230156870931926152000206026311 None
lc_ctrl_errors 107015814938042674616015261490557975611388155936186834381141270750954385718264 None
lc_ctrl_jtag_state_failure 65459823682465468511560808645338839546794385966247067287225804545685259875557 None
lc_ctrl_jtag_state_post_trans 59459048601105263647410550596641760887983120871572258908191099134722803059186 None
lc_ctrl_sec_mubi 50328119865010671702135012686447964020226913031282677061421026426302289292154 None
lc_ctrl_stress_all 49833011731923196547214554475966225979070824616937667001769358224765089855096 None
lc_ctrl_stress_all_with_rand_reset 86583405547840908216502135533079112194533178225036915321703220394655097731581 None
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 55469466948174627165946997268808785881370839832831017864598721707154855544623 176
UVM_INFO @ 51824024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---