Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.19 %
  • code
  • 89.72 %
  • assert
  • 96.69 %
  • func
  • 75.16 %
  • block
  • 96.16 %
  • line
  • 96.52 %
  • branch
  • 90.27 %
  • toggle
  • 79.21 %
  • FSM
  • 92.86 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 29.955us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 109.234us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 92.871us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 124.928us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.538us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.000s 99.439us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 92.871us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 4506.337us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 13.298us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 9.000s 583.493us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 528.259us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 2.000s 64.360us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.000s 1015.232us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 1251.477us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 229.992us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.000s 2916.986us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.000s 1401.353us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 71.690us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 129.802us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 91.681us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 250.587us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 159.287us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.063s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 17.315us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 741.003us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 741.003us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 109.234us 1 1 100.00
lc_ctrl_csr_rw 2.000s 92.871us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.538us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 44.298us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 109.234us 1 1 100.00
lc_ctrl_csr_rw 2.000s 92.871us 1 1 100.00
lc_ctrl_csr_aliasing 1.000s 48.538us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 44.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 167.531us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 167.531us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.000s 4506.337us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 1745.296us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.000s 583.493us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.000s 320.557us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 302.640us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.000s 302.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 76938932643592002359813044004253220771967947064075781220299804810030676832442 None
lc_ctrl_state_post_trans 59060392393964805933185768749361154620397167024348261910142750655805357604736 None
lc_ctrl_prog_failure 82012065130941847745218081963842319815255685600708288617781034573765195930383 None
lc_ctrl_errors 83768779877775389199255875208710653985683658687333891923120896748078923774962 None
lc_ctrl_jtag_state_failure 112083502552537424834010987061490371744435148870249645370852323264173407148411 None
lc_ctrl_jtag_state_post_trans 63348918635641542767391431349082143614425345949899979431245693189418348971261 None
lc_ctrl_jtag_prog_failure 101233681435390149294242356258528804275408679142566350045742229681845348172675 None
lc_ctrl_jtag_errors 90479082495479776622999230829255801936949408922601236885533538182573754150047 None
lc_ctrl_sec_mubi 10773511635615401316031537678876655749831709872833179587478162965157381981235 None
lc_ctrl_stress_all 98270032378769293701572915217710428604213559537600920467813705214502787530523 None
lc_ctrl_stress_all_with_rand_reset 94156419301386710566692131909684410588924391258426556974457962737495604300893 None