Simulation Results: mbx

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.70 %
  • code
  • 89.50 %
  • assert
  • 97.34 %
  • func
  • 76.26 %
  • block
  • 95.61 %
  • line
  • 95.13 %
  • branch
  • 88.29 %
  • toggle
  • 85.09 %
Validation stages
V1
83.33%
V2
72.73%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 58.000s 8304.336us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 1.000s 15.664us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 1.000s 13.603us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 6.000s 1589.543us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 96.250us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 1.000s 3.570us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 1.000s 13.603us 1 1 100.00
mbx_csr_aliasing 2.000s 96.250us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 1 0.00
mbx_stress 12.000s 1076.257us 0 1 0.00
mbx_max_activity 0 1 0.00
mbx_stress_zero_delays 7.000s 937.111us 0 1 0.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 86.000s 3545.485us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 11.000s 2303.278us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 1.000s 56.657us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 1.000s 27.605us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 1.000s 0.996us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 1.000s 0.996us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.664us 1 1 100.00
mbx_csr_rw 1.000s 13.603us 1 1 100.00
mbx_csr_aliasing 2.000s 96.250us 1 1 100.00
mbx_same_csr_outstanding 1.000s 31.221us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 1.000s 15.664us 1 1 100.00
mbx_csr_rw 1.000s 13.603us 1 1 100.00
mbx_csr_aliasing 2.000s 96.250us 1 1 100.00
mbx_same_csr_outstanding 1.000s 31.221us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 2.000s 353.038us 1 1 100.00
mbx_sec_cm 1.000s 35.083us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (mbx_scoreboard.sv:500) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) RDATA read data mismatched 2 test runs
mbx_stress 57186148754564773429970833469986045236804079637008803459577624538739259417562 382
UVM_INFO @ 1076257082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_stress_zero_delays 110509700986758305199184519257603762444733043346346311053045066742903417298776 247
UVM_INFO @ 937111228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:696) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 4208291705644112617993625932354532914041541253822611191837551553041181085286 85
TL item was: req: (cip_tl_seq_item@17777) { a_addr: 'hcbac2710 a_data: 'h8199996 a_mask: 'he a_size: 'h2 a_param: 'h0 a_source: 'h83 a_opcode: 'h1 a_user: 'h245c9 d_param: 'h0 d_source: 'h83 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 996379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 102170845659468639171805415410656149618172978888241342722277991668324644561724 86
TL item was: req: (cip_tl_seq_item@18115) { a_addr: 'hfb31e790 a_data: 'h25a861c5 a_mask: 'h1 a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h1 a_user: 'h26a14 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1caa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3569749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---