Simulation Results: otbn

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.78 %
  • code
  • 81.98 %
  • assert
  • 89.49 %
  • func
  • 97.88 %
  • block
  • 97.75 %
  • line
  • 97.95 %
  • branch
  • 81.95 %
  • toggle
  • 81.81 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 13.000s 36.766us 1 1 100.00
otbn_smoke_vectorized 9.000s 73.297us 1 1 100.00
single_binary 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 17.738us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 23.079us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 9.000s 85.291us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 4.000s 63.923us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 10.000s 77.967us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 23.079us 1 1 100.00
otbn_csr_aliasing 4.000s 63.923us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 71.000s 1526.942us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 54.000s 1225.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 56.000s 154.974us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 30.000s 67.311us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 114.000s 951.592us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 23.000s 42.803us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 18.000s 78.100us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 8.000s 48.072us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 11.000s 106.449us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 7.000s 27.882us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 81.544us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 111.744us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 111.744us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 5.000s 17.738us 1 1 100.00
otbn_csr_rw 4.000s 23.079us 1 1 100.00
otbn_csr_aliasing 4.000s 63.923us 1 1 100.00
otbn_same_csr_outstanding 5.000s 128.480us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 5.000s 17.738us 1 1 100.00
otbn_csr_rw 4.000s 23.079us 1 1 100.00
otbn_csr_aliasing 4.000s 63.923us 1 1 100.00
otbn_same_csr_outstanding 5.000s 128.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 53.544us 1 1 100.00
otbn_dmem_err 10.000s 24.007us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 12.000s 105.252us 1 1 100.00
otbn_controller_ispr_rdata_err 15.000s 61.063us 1 1 100.00
otbn_mac_bignum_acc_err 11.000s 193.684us 1 1 100.00
otbn_urnd_err 11.000s 19.420us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 8.000s 11.318us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 10.000s 20.874us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 10.000s 27.776us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
otbn_tl_intg_err 27.000s 291.023us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 37.000s 94.154us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 36.766us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 24.007us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 53.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 27.000s 291.023us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 18.000s 78.100us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 53.544us 1 1 100.00
otbn_dmem_err 10.000s 24.007us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 48.072us 1 1 100.00
otbn_illegal_mem_acc 8.000s 11.318us 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 53.544us 1 1 100.00
otbn_dmem_err 10.000s 24.007us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 48.072us 1 1 100.00
otbn_illegal_mem_acc 8.000s 11.318us 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 18.000s 78.100us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 53.544us 1 1 100.00
otbn_dmem_err 10.000s 24.007us 1 1 100.00
otbn_zero_state_err_urnd 8.000s 48.072us 1 1 100.00
otbn_illegal_mem_acc 8.000s 11.318us 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 8.000s 50.634us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 56.281us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 23.000s 154.815us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 23.000s 154.815us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 46.678us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 100.257us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 19.000s 94.033us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 19.000s 94.033us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 20.000s 73.633us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 114.000s 951.592us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 16.000s 42.498us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 11.000s 63.349us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 270.000s 3346.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 186.000s 1057.848us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 55570220810352323545888083963146661583075419396437315276675169508722822249953 237
UVM_INFO @ 67310570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 1 test run
otbn_urnd_err 30395334546548434456315572795503552604044176773612792445168786388198136322055 127
UVM_ERROR @ 19420336 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 19420336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---