Simulation Results: otp_ctrl

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.97 %
  • code
  • 72.31 %
  • assert
  • 94.04 %
  • func
  • 61.57 %
  • line
  • 87.43 %
  • branch
  • 83.89 %
  • cond
  • 85.54 %
  • toggle
  • 67.19 %
  • FSM
  • 37.49 %
Validation stages
V1
100.00%
V2
70.00%
V2S
88.89%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.370s 135.395us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.920s 1297.832us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 2.370s 49.377us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 6.840s 574.633us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 13.260s 382.966us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.860s 116.244us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 2.370s 49.377us 1 1 100.00
otp_ctrl_csr_aliasing 13.260s 382.966us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 2.080s 82.350us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 2.030s 80.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 318.110s 113091.562us 0 1 0.00
init_fail 1 1 100.00
otp_ctrl_init_fail 5.370s 296.795us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 16.460s 1391.741us 0 1 0.00
otp_ctrl_check_fail 17.460s 1923.888us 1 1 100.00
regwen_during_otp_init 0 1 0.00
otp_ctrl_regwen 4.630s 131.277us 0 1 0.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 21.050s 1967.907us 1 1 100.00
lc_interactions 1 2 50.00
otp_ctrl_parallel_lc_req 10.350s 757.114us 0 1 0.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_dai_errors 0 1 0.00
otp_ctrl_dai_errs 7.800s 368.395us 0 1 0.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 24.780s 1380.436us 1 1 100.00
test_access 0 1 0.00
otp_ctrl_test_access 8.620s 439.747us 0 1 0.00
stress_all 1 1 100.00
otp_ctrl_stress_all 14.910s 750.871us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 2.430s 91.261us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.430s 198.458us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.780s 360.019us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.780s 360.019us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.920s 1297.832us 1 1 100.00
otp_ctrl_csr_rw 2.370s 49.377us 1 1 100.00
otp_ctrl_csr_aliasing 13.260s 382.966us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.160s 288.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.920s 1297.832us 1 1 100.00
otp_ctrl_csr_rw 2.370s 49.377us 1 1 100.00
otp_ctrl_csr_aliasing 13.260s 382.966us 1 1 100.00
otp_ctrl_same_csr_outstanding 3.160s 288.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
otp_ctrl_tl_intg_err 17.380s 1812.401us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 17.380s 1812.401us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_ctrl_macro_errs 24.780s 1380.436us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_ctrl_macro_errs 24.780s 1380.436us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 8.960s 507.114us 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 5.370s 296.795us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 17.460s 1923.888us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 20.370s 1492.574us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 447.670s 73760.456us 1 1 100.00
sec_cm_direct_access_config_regwen 0 1 0.00
otp_ctrl_regwen 4.630s 131.277us 0 1 0.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 9.990s 329.631us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 24.780s 1380.436us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 104.270s 62753.916us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 40.630s 2693.292us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 3 test runs
otp_ctrl_background_chks 50234561788122682471592926720060706136146415251672216571949025557695999685254 5008
UVM_INFO @ 1391740908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_test_access 37901232876231508121928587431763081675837451952010518898118446448227177194791 4280
UVM_INFO @ 439746551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 45114027627758277213203212761310302603617739605039844000296331078004573718218 7734
UVM_INFO @ 2693292105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_partition_walk_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_partition_walk 50166866179613849911090726660372013724419280838628014458082749701241213928578 112820
UVM_INFO @ 113091561609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_low_freq_read 19181662015222524305220545544071063398118225400311539721182441109095855677701 100
UVM_INFO @ 62753915521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:961) [scoreboard] Check failed (csr.get_mirrored_value() | status_mask) == (item.d_data | status_mask) (* [*] vs * [*]) reg name: status, compare_mask * 1 test run
otp_ctrl_parallel_lc_req 5997858130246545634842715439116456896586119206096160855129864179597327171495 8463
UVM_INFO @ 757114015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_dai_errs 21167703647299654162639594548398724641924036670270666636499880143643456309129 5555
UVM_INFO @ 368395284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: otp_ctrl_core_reg_block.status.dai_idle reset value: * 1 test run
otp_ctrl_regwen 81528628979398986885684749001118254969658093045799450969103699145085570949729 2877
UVM_INFO @ 131276899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---