Simulation Results: rom_ctrl/32kb

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.25 %
  • code
  • 79.25 %
  • assert
  • 97.53 %
  • func
  • 90.97 %
  • block
  • 77.99 %
  • line
  • 78.48 %
  • branch
  • 77.91 %
  • toggle
  • 84.44 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
77.78%
V2S
66.67%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.000s 1099.411us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 68.739us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 2.000s 74.815us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 163.189us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 78.234us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 2.000s 66.606us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 2.000s 74.815us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 78.234us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 104.789us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 56.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 2.000s 8.666us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 4.000s 127.962us 1 1 100.00
kmac_err_chk 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
rom_ctrl_alert_test 2.000s 83.972us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 131.231us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.000s 131.231us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 68.739us 1 1 100.00
rom_ctrl_csr_rw 2.000s 74.815us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 78.234us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 57.026us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.000s 68.739us 1 1 100.00
rom_ctrl_csr_rw 2.000s 74.815us 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 78.234us 1 1 100.00
rom_ctrl_same_csr_outstanding 2.000s 57.026us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 1040.791us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 132.000s 2506.303us 1 1 100.00
rom_ctrl_tl_intg_err 17.000s 175.833us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 132.000s 2506.303us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 132.000s 2506.303us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 132.000s 2506.303us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 132.000s 2506.303us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.000s 1099.411us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.000s 1099.411us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.000s 1099.411us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 17.000s 175.833us 1 1 100.00
sec_cm_bus_local_esc 0 2 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 3600.000s 0.000us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 10.000s 1040.791us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 132.000s 2506.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 56203270586802110702019445441691416117089181978895282878277172365852488127568 None
rom_ctrl_kmac_err_chk 105540173764309281940888495505800757509462403183948356508390587790000459602859 None
rom_ctrl_stress_all_with_rand_reset 89925401597155240383076035640340762405443897391572551819728228421732561435649 None
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 23796487504485600004383127572886913589283649161438249931766057133643515901770 88
UVM_INFO @ 8666096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---