Simulation Results: rstmgr

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.88 %
  • code
  • 99.32 %
  • assert
  • 98.53 %
  • func
  • 95.78 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 98.86 %
  • toggle
  • 99.52 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.440s 69.124us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.620s 91.325us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.250s 37.359us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.480s 81.756us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.470s 38.067us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.750s 97.461us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.250s 37.359us 1 1 100.00
rstmgr_csr_aliasing 1.470s 38.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 2.250s 201.150us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.640s 51.588us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.530s 79.010us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 6.220s 538.917us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 6.220s 538.917us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 6.220s 538.917us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 6.220s 538.917us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 16.250s 1979.923us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.230s 38.076us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 3.040s 73.769us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 3.040s 73.769us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.620s 91.325us 1 1 100.00
rstmgr_csr_rw 1.250s 37.359us 1 1 100.00
rstmgr_csr_aliasing 1.470s 38.067us 1 1 100.00
rstmgr_same_csr_outstanding 1.730s 74.793us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.620s 91.325us 1 1 100.00
rstmgr_csr_rw 1.250s 37.359us 1 1 100.00
rstmgr_csr_aliasing 1.470s 38.067us 1 1 100.00
rstmgr_same_csr_outstanding 1.730s 74.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 31.430s 3673.015us 1 1 100.00
rstmgr_tl_intg_err 5.930s 620.037us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 31.430s 3673.015us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 31.430s 3673.015us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 5.930s 620.037us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.540s 59.811us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 6.100s 477.804us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 3.360s 291.717us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 31.430s 3673.015us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 37.359us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.250s 37.359us 1 1 100.00