Simulation Results: rv_dm/use_dmi_interface

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 86.98 %
  • code
  • 74.93 %
  • assert
  • 96.43 %
  • func
  • 89.58 %
  • block
  • 89.36 %
  • line
  • 89.06 %
  • branch
  • 71.10 %
  • toggle
  • 77.06 %
  • FSM
  • 62.50 %
Validation stages
V1
92.59%
V2
69.57%
V2S
85.71%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 38.000s 1218.681us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 49.000s 383.192us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 44.000s 430.358us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 59.000s 12656.533us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 36.000s 1036.535us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 55.000s 10898.725us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 51.000s 4333.222us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 52.000s 7961.071us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 62.000s 24999.814us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 49.000s 480.702us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 46.000s 302.974us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 46.000s 237.819us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 51.000s 257.198us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 44.000s 85.037us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 50.000s 2649.885us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 51.000s 124.476us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 46.000s 511.597us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 49.000s 480.702us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 49.000s 418.379us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 45.000s 480.289us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 46.000s 237.819us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 48.000s 68.089us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 45.000s 139.307us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 41.000s 106.427us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 88.000s 6592.395us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 69.000s 1079.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 41.000s 275.670us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 69.000s 1079.143us 1 1 100.00
rv_dm_csr_rw 41.000s 106.427us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 39.000s 72.690us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 45.000s 101.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 38.000s 1218.681us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 37.000s 481.192us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 43.000s 136.355us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 48.000s 354.863us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 48.000s 2570.200us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 59.000s 13470.908us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 41.000s 308.457us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 46.000s 667.018us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 47.000s 6411.896us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 44.000s 76.485us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 37.000s 1486.032us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 45.000s 233.022us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 51.000s 97.834us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 59.000s 7093.336us 1 1 100.00
rv_dm_tap_fsm_rand_reset 56.000s 3060.946us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 45.000s 132.488us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 45.000s 926.791us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 41.000s 43.689us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 47.000s 204.179us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 47.000s 204.179us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 69.000s 1079.143us 1 1 100.00
rv_dm_csr_hw_reset 45.000s 139.307us 1 1 100.00
rv_dm_csr_rw 41.000s 106.427us 1 1 100.00
rv_dm_same_csr_outstanding 51.000s 358.871us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 69.000s 1079.143us 1 1 100.00
rv_dm_csr_hw_reset 45.000s 139.307us 1 1 100.00
rv_dm_csr_rw 41.000s 106.427us 1 1 100.00
rv_dm_same_csr_outstanding 51.000s 358.871us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_sec_cm 45.000s 1134.470us 1 1 100.00
rv_dm_tl_intg_err 54.000s 2053.206us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 54.000s 2053.206us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 37.000s 1486.032us 1 1 100.00
rv_dm_debug_disabled 47.000s 135.426us 0 1 0.00
sec_cm_lc_dft_en_intersig_mubi 1 2 50.00
rv_dm_sba_debug_disabled 37.000s 1486.032us 1 1 100.00
rv_dm_debug_disabled 47.000s 135.426us 0 1 0.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 38.000s 1218.681us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 50.000s 158.361us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 43.000s 97.817us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 43.000s 97.817us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 50.000s 158.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 45.000s 288.865us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 225.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 64814372473374481257008086759541113614173475440018189849161903434545597750986 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23799
rv_dm_autoincr_sba_tl_access 77828604431547450639998945207284760162073447961518781656957750395180902835215 132
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23908
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 2 test runs
rv_dm_delayed_resp_sba_tl_access 45205027148639193588084985129941734261734426848992844015335739711038928860396 107
UVM_INFO @ 308457273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_bad_sba_tl_access 54425794352794522163684856020888998899447538842891824670593213918266807243078 107
UVM_INFO @ 667018123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 83442617941244336353810809804466678882421005487260027744828765696412336448890 87
UVM_INFO @ 97833543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all_with_rand_reset 107919033134660969404769829871180408892377480885262797093288624735185843645706 91
UVM_INFO @ 288865382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 2 test runs
rv_dm_jtag_dmi_debug_disabled 14220886514912767791851987176797943066846080019615486236376964238173435327825 87
UVM_INFO @ 76485462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 86899282613600144993969708789533831828456514023079255185642265632057679329828 89
UVM_INFO @ 926790963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 44091672571485138370790937290418315605041406464538213183107919304266892499760 87
UVM_INFO @ 257197866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@23859) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 35327849943055346410858999624945277796475666646242385159713213445916109149309 87
).
UVM_INFO @ 68089434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_debug_disabled_vseq.sv:33) [rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) 1 test run
rv_dm_debug_disabled 114857581672773672563067024848908552771441572081829532014229069619206242985107 91
UVM_INFO @ 135425631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 74477834808877826453835531522576465378731526656694005067666471696138264053342 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---