Simulation Results: rv_timer

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 97.74 %
  • code
  • 95.85 %
  • assert
  • 97.78 %
  • func
  • 99.58 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.000s 231.684us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 70.375us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 2.000s 21.960us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 5.000s 1569.626us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 30.890us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 70.422us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 2.000s 21.960us 1 1 100.00
rv_timer_csr_aliasing 1.000s 30.890us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 1 100.00
rv_timer_random_reset 2.000s 271.133us 1 1 100.00
disabled 1 1 100.00
rv_timer_disabled 2.000s 1758.513us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 40.000s 36007.540us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 40.000s 36007.540us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 10.000s 839.237us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 1.000s 12.580us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 1.000s 11.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 3.000s 208.686us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 3.000s 208.686us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 70.375us 1 1 100.00
rv_timer_csr_rw 2.000s 21.960us 1 1 100.00
rv_timer_csr_aliasing 1.000s 30.890us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 29.654us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 1.000s 70.375us 1 1 100.00
rv_timer_csr_rw 2.000s 21.960us 1 1 100.00
rv_timer_csr_aliasing 1.000s 30.890us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 29.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.000s 40.940us 1 1 100.00
rv_timer_tl_intg_err 2.000s 202.857us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 2.000s 202.857us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.000s 242.935us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 2.000s 170.249us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 22.000s 3803.580us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_min 100755593281910091741017392615671114794771591078491862599566514748219991712528 84
UVM_INFO @ 242934571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 50917058540303085901663679330527305726619440326487560734191882450269003241699 84
UVM_INFO @ 170249212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---