Simulation Results: spi_device/1r1w

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 85.18 %
  • code
  • 92.38 %
  • assert
  • 95.27 %
  • func
  • 67.89 %
  • block
  • 98.36 %
  • line
  • 98.76 %
  • branch
  • 97.03 %
  • toggle
  • 85.17 %
  • FSM
  • 88.54 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 128.000s 20362.095us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 2.000s 137.093us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 3.000s 39.402us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 15.000s 950.012us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 19.000s 3564.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 5.000s 248.040us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 3.000s 39.402us 1 1 100.00
spi_device_csr_aliasing 19.000s 3564.947us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 1.000s 33.966us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 2.000s 36.914us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 40.559us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 2.379us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 3.883us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 7.000s 1048.732us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 7.000s 1048.732us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 6.000s 804.092us 1 1 100.00
spi_device_tpm_sts_read 2.000s 61.176us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 15.000s 947.705us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.000s 462.115us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 405.419us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 6.000s 405.419us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 25.000s 11285.401us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 25.000s 11285.401us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 25.000s 11285.401us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 25.000s 11285.401us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 25.000s 11285.401us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 4.000s 358.265us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 65.000s 4674.038us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 65.000s 4674.038us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 65.000s 4674.038us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 33.000s 8104.354us 1 1 100.00
spi_device_read_buffer_direct 4.000s 114.973us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 65.000s 4674.038us 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 193.000s 67066.692us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 310.354us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 310.354us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 12.000s 1342.294us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 128.000s 20362.095us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 53.000s 6445.985us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 631.000s 692719.326us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 2.000s 35.493us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.000s 58.611us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 198.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 198.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 137.093us 1 1 100.00
spi_device_csr_rw 3.000s 39.402us 1 1 100.00
spi_device_csr_aliasing 19.000s 3564.947us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 46.027us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 2.000s 137.093us 1 1 100.00
spi_device_csr_rw 3.000s 39.402us 1 1 100.00
spi_device_csr_aliasing 19.000s 3564.947us 1 1 100.00
spi_device_same_csr_outstanding 3.000s 46.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 2.000s 70.814us 1 1 100.00
spi_device_tl_intg_err 20.000s 673.336us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 20.000s 673.336us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 57413979522757467488632424117211519424771407466446893317284008218570064602217 87
UVM_ERROR @ 1700699 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975] not found within the scope .
UVM_ERROR @ 1700699 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 6689443565224723939946888952807149539418713769755738800232027785877839767709 85
UVM_ERROR @ 1254002 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3b6 [1110110110] vs 0x0 [0])
UVM_ERROR @ 1297002 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x84 [10000100] vs 0x0 [0])
UVM_ERROR @ 1350002 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x37a [1101111010] vs 0x0 [0])
UVM_ERROR @ 1375002 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1ee [111101110] vs 0x0 [0])