Simulation Results: spi_host

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 92.48 %
  • code
  • 95.06 %
  • assert
  • 94.14 %
  • func
  • 88.24 %
  • block
  • 97.01 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 3.000s 110.234us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 38.713us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 25.326us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 45.157us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 32.525us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 28.259us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 25.326us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.525us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 15.206us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 25.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 25.731us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 6.000s 678.133us 1 1 100.00
spi_host_error_cmd 1.000s 17.872us 1 1 100.00
spi_host_event 10.000s 2354.792us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 4.000s 192.725us 1 1 100.00
speed 1 1 100.00
spi_host_speed 4.000s 192.725us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 4.000s 192.725us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 15.000s 420.109us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 241.126us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 24.553us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 4.000s 192.725us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 4.000s 192.725us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 3.000s 110.234us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 3.000s 110.234us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 1.000s 58.228us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 419.205us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 73.000s 4092.704us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 87.113us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 6.000s 678.133us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 26.012us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 18.713us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 136.788us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 136.788us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 38.713us 1 1 100.00
spi_host_csr_rw 1.000s 25.326us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.525us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 35.087us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 38.713us 1 1 100.00
spi_host_csr_rw 1.000s 25.326us 1 1 100.00
spi_host_csr_aliasing 2.000s 32.525us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 35.087us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 185.335us 1 1 100.00
spi_host_sec_cm 1.000s 161.322us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 185.335us 1 1 100.00