Simulation Results: sram_ctrl/main

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 96.21 %
  • code
  • 96.15 %
  • assert
  • 97.69 %
  • func
  • 94.80 %
  • block
  • 94.48 %
  • line
  • 95.64 %
  • branch
  • 92.86 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 786.117us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 41.954us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.958us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 423.694us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.680us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 725.037us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 43.958us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.680us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 272.000s 45410.089us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 125.000s 11847.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 38.000s 20257.400us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 129.000s 7659.425us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 219.000s 15185.511us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 98.000s 73033.734us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 52.000s 43144.823us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 34.000s 4975.066us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1403.684us 1 1 100.00
sram_ctrl_partial_access_b2b 318.000s 76511.225us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 6.000s 690.449us 1 1 100.00
sram_ctrl_throughput_w_partial_write 6.000s 1399.918us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 676.749us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 17.000s 2063.802us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 1866.585us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 541.000s 125261.355us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 43.958us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 84.706us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 84.706us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 41.954us 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.958us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.680us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.291us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 41.954us 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.958us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 25.680us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 16.291us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7065.430us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1467.184us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 201.659us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1467.184us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 201.659us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 17.000s 2063.802us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 17.000s 2063.802us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 43.958us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 34.000s 4975.066us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 34.000s 4975.066us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 34.000s 4975.066us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 52.000s 43144.823us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 28.000s 7065.430us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 786.117us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 786.117us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 34.000s 4975.066us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1467.184us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 52.000s 43144.823us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1467.184us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1467.184us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 786.117us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1467.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.000s 1761.448us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 57942127611291996744801082703788122224801431351352110084785143166356881439116 None
sram_ctrl_mubi_enc_err 8463661932906155704847444896059158743775323005375542220939979855222180059732 None