Simulation Results: sram_ctrl/ret

 
20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.81 %
  • code
  • 82.63 %
  • assert
  • 97.81 %
  • func
  • 95.00 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 81.83 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 45.442us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 13.855us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.092us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 117.045us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.366us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 97.639us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 18.092us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.366us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 10.000s 387.106us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 392.089us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 2.000s 88.524us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 138.000s 26135.676us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 546.115us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 17.000s 1829.849us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2310.313us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 11.000s 5799.081us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 442.694us 1 1 100.00
sram_ctrl_partial_access_b2b 294.000s 20509.233us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 62.464us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 37.035us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 80.804us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 5.000s 112.008us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 97.362us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 48.000s 3179.311us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 14.351us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 56.418us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 56.418us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 13.855us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.092us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.366us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 36.110us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 13.855us 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.092us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 17.366us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 36.110us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 206.173us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 2547.543us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 237.595us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 2547.543us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 237.595us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 112.008us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 5.000s 112.008us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 18.092us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 11.000s 5799.081us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 5799.081us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 11.000s 5799.081us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2310.313us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3601.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 206.173us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.442us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 45.442us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 11.000s 5799.081us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 2547.543us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 7.000s 2310.313us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 2547.543us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 2547.543us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 45.442us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 2547.543us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 77.000s 6103.695us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 33403008308281217062197969188213535078580956373247135785905187505464174457081 None
sram_ctrl_mubi_enc_err 111871375994502638010234783162587386052244705414924216199997529895792439879690 None