Simulation Results

Simulation Results: uart

20/08/2026 21:24:37 DVSim: v1.51.0 sha: 421e9c8 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
94.82 %

code
96.65 %

assert
97.12 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
88.74 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	18.000s	5449.012us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	18.839us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	2.000s	41.762us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.000s	294.473us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	25.192us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	1.000s	299.873us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	2.000s	41.762us	1	1	100.00
	uart_csr_aliasing	1.000s	25.192us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	37.000s	38486.727us	1	1	100.00
parity				2	2	100.00
	uart_smoke	18.000s	5449.012us	1	1	100.00
	uart_tx_rx	37.000s	38486.727us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	62.000s	36108.900us	1	1	100.00
	uart_rx_parity_err	136.000s	101333.274us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	37.000s	38486.727us	1	1	100.00
	uart_intr	62.000s	36108.900us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	90.000s	54329.974us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	57.000s	30390.169us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	92.000s	46105.869us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	62.000s	36108.900us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	62.000s	36108.900us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	62.000s	36108.900us	1	1	100.00
perf				1	1	100.00
	uart_perf	68.000s	8093.797us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	23.000s	4434.274us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	23.000s	4434.274us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	32.000s	15638.110us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	5.000s	4413.039us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	4.000s	1614.944us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	11.000s	6455.803us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	485.000s	122650.783us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	213.000s	82001.712us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	1.000s	12.359us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	1.000s	52.632us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	2.000s	83.636us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	2.000s	83.636us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	1.000s	18.839us	1	1	100.00
	uart_csr_rw	2.000s	41.762us	1	1	100.00
	uart_csr_aliasing	1.000s	25.192us	1	1	100.00
	uart_same_csr_outstanding	2.000s	17.326us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	1.000s	18.839us	1	1	100.00
	uart_csr_rw	2.000s	41.762us	1	1	100.00
	uart_csr_aliasing	1.000s	25.192us	1	1	100.00
	uart_same_csr_outstanding	2.000s	17.326us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_sec_cm	1.000s	42.140us	1	1	100.00
	uart_tl_intg_err	2.000s	97.018us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	2.000s	97.018us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	uart_stress_all_with_rand_reset	17.000s	1407.371us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				1 test run
	uart_noise_filter	71149585832632945043612322189437095998882190733767347752572602478424105312291	89	UVM_ERROR @ 15582069766 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 15583196048 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 15622215930 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 15622594866 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0