Simulation Results: ac_range_check

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.89 %
  • code
  • 93.00 %
  • assert
  • 97.75 %
  • func
  • 57.93 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 80.82 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 40.000s 9970.136us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 49.000s 10538.636us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 10.000s 111.708us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 11.000s 150.615us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 41.000s 714.925us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 29.000s 2122.264us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 49.391us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 11.000s 150.615us 1 1 100.00
ac_range_check_csr_aliasing 29.000s 2122.264us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 11.000s 447.138us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 37.000s 1972.376us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 187.000s 6472.825us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 10.000s 26.544us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 10.000s 14.454us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 4.000s 213.828us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 4.000s 213.828us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 111.708us 1 1 100.00
ac_range_check_csr_rw 11.000s 150.615us 1 1 100.00
ac_range_check_csr_aliasing 29.000s 2122.264us 1 1 100.00
ac_range_check_same_csr_outstanding 12.000s 54.574us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 111.708us 1 1 100.00
ac_range_check_csr_rw 11.000s 150.615us 1 1 100.00
ac_range_check_csr_aliasing 29.000s 2122.264us 1 1 100.00
ac_range_check_same_csr_outstanding 12.000s 54.574us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 22.000s 2048.666us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 22.000s 2048.666us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 22.000s 2048.666us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 22.000s 2048.666us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 143.000s 21486.359us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 10.000s 14.171us 1 1 100.00
ac_range_check_tl_intg_err 7.000s 118.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 321.000s 2296.912us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 40.000s 2654.226us 1 1 100.00