Simulation Results: aes/gcm_unmasked

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.15 %
  • code
  • 91.06 %
  • assert
  • 97.75 %
  • func
  • 60.65 %
  • block
  • 91.25 %
  • line
  • 93.07 %
  • branch
  • 84.53 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 85.948us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 60.745us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 70.583us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 129.832us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 7.000s 891.530us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 323.461us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 144.376us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 129.832us 1 1 100.00
aes_csr_aliasing 3.000s 323.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 60.745us 1 1 100.00
aes_config_error 3.000s 117.092us 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 60.745us 1 1 100.00
aes_config_error 3.000s 117.092us 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 67.834us 1 1 100.00
aes_b2b 5.000s 162.339us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 60.745us 1 1 100.00
aes_config_error 3.000s 117.092us 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
aes_alert_reset 2.000s 69.913us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 77.858us 1 1 100.00
aes_config_error 3.000s 117.092us 1 1 100.00
aes_alert_reset 2.000s 69.913us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 318.142us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 6.000s 127.360us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 69.913us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 67.834us 1 1 100.00
aes_sideload 2.000s 76.491us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 475.282us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 4.000s 108.515us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 51.306us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 64.978us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 64.978us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 70.583us 1 1 100.00
aes_csr_rw 2.000s 129.832us 1 1 100.00
aes_csr_aliasing 3.000s 323.461us 1 1 100.00
aes_same_csr_outstanding 2.000s 197.139us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 70.583us 1 1 100.00
aes_csr_rw 2.000s 129.832us 1 1 100.00
aes_csr_aliasing 3.000s 323.461us 1 1 100.00
aes_same_csr_outstanding 2.000s 197.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 355.315us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 826.011us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 814.536us 1 1 100.00
aes_tl_intg_err 3.000s 137.106us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 137.106us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 69.913us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 60.745us 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
aes_alert_reset 2.000s 69.913us 1 1 100.00
aes_core_fi 3.000s 66.516us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 117.092us 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
aes_core_fi 3.000s 66.516us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 85.452us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 120.744us 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 67.834us 1 1 100.00
aes_sideload 2.000s 76.491us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 120.744us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 120.744us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 120.744us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 120.744us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 120.744us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 67.834us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3602.041s 0.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
aes_ctr_fi 2.000s 64.196us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3602.041s 0.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3602.041s 0.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_ctr_fi 2.000s 64.196us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3602.041s 0.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
aes_ctr_fi 2.000s 64.196us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 69.913us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
aes_ctr_fi 2.000s 64.196us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
aes_ctr_fi 2.000s 64.196us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_ctr_fi 2.000s 64.196us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3602.041s 0.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3602.041s 0.000us 0 1 0.00
aes_control_fi 2.000s 80.289us 1 1 100.00
aes_cipher_fi 2.000s 64.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 324.232us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 80455209746415391356289546288794461294620921837501273435293689489865053808461 8890
UVM_INFO @ 108514762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 107951844398984561454434094927702510331769028037018920600070737400867656125577 531
UVM_INFO @ 324231677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_fi 25598957004564027492226002203420361533142239621367737642202585363654590654274 None