Simulation Results: clkmgr

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.91 %
  • code
  • 69.26 %
  • assert
  • 88.84 %
  • func
  • 72.63 %
  • line
  • 82.22 %
  • branch
  • 87.53 %
  • cond
  • 77.13 %
  • toggle
  • 99.43 %
  • FSM
  • 0.00 %
Validation stages
V1
33.33%
V2
53.85%
V2S
37.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 2.470s 100.292us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.740s 59.922us 1 1 100.00
csr_rw 0 1 0.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 4.550s 302.726us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 1.090s 9.775us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.040s 8.873us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 0 2 0.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
clkmgr_csr_aliasing 1.090s 9.775us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.080s 30.222us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.290s 26.198us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.370s 44.379us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 2.470s 100.292us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 1.020s 8.123us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.880s 4.018us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 1.020s 8.123us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 0.680s 8.438us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.190s 23.195us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 3.200s 42.455us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 3.200s 42.455us 1 1 100.00
tl_d_outstanding_access 1 4 25.00
clkmgr_csr_hw_reset 1.740s 59.922us 1 1 100.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
clkmgr_csr_aliasing 1.090s 9.775us 0 1 0.00
clkmgr_same_csr_outstanding 0.880s 2.675us 0 1 0.00
tl_d_partial_access 1 4 25.00
clkmgr_csr_hw_reset 1.740s 59.922us 1 1 100.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
clkmgr_csr_aliasing 1.090s 9.775us 0 1 0.00
clkmgr_same_csr_outstanding 0.880s 2.675us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 3.090s 159.987us 1 1 100.00
clkmgr_tl_intg_err 1.040s 11.318us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 137.601us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 137.601us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 137.601us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 137.601us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.910s 3.105us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 1.040s 11.318us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 1.020s 8.123us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.880s 4.018us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.160s 137.601us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.380s 58.557us 1 1 100.00
sec_cm_jitter_config_mubi 0 1 0.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 3.090s 159.987us 1 1 100.00
sec_cm_meas_config_regwen 0 1 0.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
sec_cm_clk_ctrl_config_regwen 0 1 0.00
clkmgr_csr_rw 0.970s 8.341us 0 1 0.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 3.090s 159.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 1.030s 13.733us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 3.890s 164.893us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 4 test runs
clkmgr_tl_intg_err 68843076278380637768869919532592945699972142582236228507236523252987382311358 92
UVM_INFO @ 11317863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_rw 90319669035832331037833583490750716821883720608386614679007251835661137797613 81
UVM_INFO @ 8341380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_aliasing 100069923130424466293566759206895460910228743092521667544454346143003643709825 81
UVM_INFO @ 9775145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 39563053616382898645790500062635347393633917996179614198290683314272432683835 82
UVM_INFO @ 8873046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 3 test runs
clkmgr_frequency 12745099200529935450851255865854430348625373050304930967412346631617863059452 82
UVM_INFO @ 8122936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 1820754999571843232401863187587938958194575941661694766122291140081051108965 147
UVM_INFO @ 164893006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 18262173876008467071455076677582886361594002234610157972072517832699128528826 82
UVM_INFO @ 8438339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 1 test run
clkmgr_frequency_timeout 65547373250122596870634294531795767837916384062429959094574616009384945919012 84
UVM_INFO @ 4018266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en 1 test run
clkmgr_regwen 13983770654119667162346207902777060223375516441210186468555619966583181589310 80
UVM_INFO @ 13733024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 109161093361249157696707842517761787459889828535975554448708529035506305005834 81
UVM_INFO @ 3104591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 13740049754962446091127217866199326774618988897758141577519949078466663205474 81
UVM_INFO @ 302726104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 51635329072614443584756332228170414442951815567290343282523241077135343296211 81
UVM_INFO @ 2674911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---