Simulation Results: csrng

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.22 %
  • code
  • 92.31 %
  • assert
  • 94.32 %
  • func
  • 75.03 %
  • block
  • 96.95 %
  • line
  • 97.73 %
  • branch
  • 92.43 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 61.420us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 5.000s 277.324us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 39.794us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 23.000s 1140.310us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 55.570us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 53.789us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 39.794us 1 1 100.00
csrng_csr_aliasing 4.000s 55.570us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
alerts 1 1 100.00
csrng_alert 16.000s 279.154us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 177.410us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 177.410us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 311.000s 4782.698us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 3.000s 112.115us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 37.341us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 29.179us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 29.179us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 5.000s 277.324us 1 1 100.00
csrng_csr_rw 2.000s 39.794us 1 1 100.00
csrng_csr_aliasing 4.000s 55.570us 1 1 100.00
csrng_same_csr_outstanding 3.000s 24.001us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 5.000s 277.324us 1 1 100.00
csrng_csr_rw 2.000s 39.794us 1 1 100.00
csrng_csr_aliasing 4.000s 55.570us 1 1 100.00
csrng_same_csr_outstanding 3.000s 24.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
csrng_tl_intg_err 6.000s 112.699us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 48.706us 1 1 100.00
csrng_csr_rw 2.000s 39.794us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 16.000s 279.154us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 311.000s 4782.698us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 16.000s 279.154us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 311.000s 4782.698us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 16.000s 279.154us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 6.000s 112.699us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
csrng_sec_cm 3.000s 146.785us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 91.649us 1 1 100.00
csrng_err 3.000s 73.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 4.000s 53.932us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:667) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 81370299146719594390817907481928710302835211294719086072164389029149364147084 100
UVM_INFO @ 177409984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:173) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 21521611693271928907823478863757651973691804037146245520412637912895282984035 109
UVM_INFO @ 53931584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---