Simulation Results: dma

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 81.51 %
  • code
  • 90.03 %
  • assert
  • 96.61 %
  • func
  • 57.89 %
  • block
  • 97.34 %
  • line
  • 96.85 %
  • branch
  • 95.76 %
  • toggle
  • 77.37 %
  • FSM
  • 90.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 4.000s 1255.731us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 293.862us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 678.356us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 22.637us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 29.122us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 10.000s 959.657us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 7.000s 156.582us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 160.870us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 29.122us 1 1 100.00
dma_csr_aliasing 7.000s 156.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 51.000s 4470.756us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 175.000s 40472.982us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 420.000s 33631.820us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 420.000s 33631.820us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 175.000s 40472.982us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 165.000s 9088.643us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 420.000s 33631.820us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 6.000s 321.750us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 51.000s 4271.364us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 41.270us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 2.000s 12.286us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 262.523us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 262.523us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 2.000s 22.637us 1 1 100.00
dma_csr_rw 2.000s 29.122us 1 1 100.00
dma_csr_aliasing 7.000s 156.582us 1 1 100.00
dma_same_csr_outstanding 4.000s 239.973us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 2.000s 22.637us 1 1 100.00
dma_csr_rw 2.000s 29.122us 1 1 100.00
dma_csr_aliasing 7.000s 156.582us 1 1 100.00
dma_same_csr_outstanding 4.000s 239.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 14.000s 205.524us 1 1 100.00
dma_generic_stress 165.000s 9088.643us 1 1 100.00
dma_handshake_stress 420.000s 33631.820us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 9.000s 1012.471us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 99.693us 1 1 100.00
dma_sec_cm 1.000s 10.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 133.000s 5433.899us 1 1 100.00
dma_longer_transfer 6.000s 762.326us 1 1 100.00
dma_stress_all_with_rand_reset 14.000s 3254.501us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 73588666965934305436310759817401058770885856766870230922236551973178118590072 100
UVM_INFO @ 3254500726ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---