Simulation Results: edn/edn0

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 76.74 %
  • code
  • 84.56 %
  • assert
  • 96.02 %
  • func
  • 49.65 %
  • block
  • 94.43 %
  • line
  • 97.17 %
  • branch
  • 88.01 %
  • toggle
  • 69.35 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 2.000s 15.400us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 28.550us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.000s 52.476us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 954.453us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 21.183us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.000s 299.481us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.000s 52.476us 1 1 100.00
edn_csr_aliasing 2.000s 21.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 2.000s 195.328us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 2.000s 195.328us 1 1 100.00
genbits 1 1 100.00
edn_genbits 2.000s 195.328us 1 1 100.00
interrupts 1 1 100.00
edn_intr 2.000s 31.546us 1 1 100.00
alerts 1 1 100.00
edn_alert 2.000s 30.049us 1 1 100.00
errs 1 1 100.00
edn_err 2.000s 27.013us 1 1 100.00
disable 2 2 100.00
edn_disable 2.000s 22.804us 1 1 100.00
edn_disable_auto_req_mode 2.000s 34.014us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 12.000s 783.537us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 2.000s 31.261us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 46.371us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 4.000s 281.858us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 4.000s 281.858us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 2.000s 28.550us 1 1 100.00
edn_csr_rw 1.000s 52.476us 1 1 100.00
edn_csr_aliasing 2.000s 21.183us 1 1 100.00
edn_same_csr_outstanding 2.000s 79.453us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 2.000s 28.550us 1 1 100.00
edn_csr_rw 1.000s 52.476us 1 1 100.00
edn_csr_aliasing 2.000s 21.183us 1 1 100.00
edn_same_csr_outstanding 2.000s 79.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 12.000s 3759.710us 1 1 100.00
edn_tl_intg_err 3.000s 206.873us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 2.000s 19.984us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 2.000s 30.049us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 12.000s 3759.710us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 12.000s 3759.710us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 12.000s 3759.710us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 12.000s 3759.710us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 2.000s 30.049us 1 1 100.00
edn_sec_cm 12.000s 3759.710us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 2.000s 30.049us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 3.000s 206.873us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 8.000s 1420.016us 1 1 100.00