Simulation Results: edn/edn1

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.25 %
  • code
  • 83.09 %
  • assert
  • 96.88 %
  • func
  • 78.78 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 88.62 %
  • toggle
  • 87.61 %
  • FSM
  • 47.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.180s 44.699us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.170s 52.135us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.130s 13.899us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.670s 47.158us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.830s 150.091us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.310s 27.449us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.130s 13.899us 1 1 100.00
edn_csr_aliasing 1.830s 150.091us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.580s 35.744us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.580s 35.744us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.580s 35.744us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.180s 36.958us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.510s 60.808us 1 1 100.00
errs 1 1 100.00
edn_err 1.310s 21.072us 1 1 100.00
disable 2 2 100.00
edn_disable 1.200s 14.516us 1 1 100.00
edn_disable_auto_req_mode 1.250s 61.158us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.860s 26.757us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.200s 126.030us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.270s 32.535us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.640s 70.716us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.640s 70.716us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.170s 52.135us 1 1 100.00
edn_csr_rw 1.130s 13.899us 1 1 100.00
edn_csr_aliasing 1.830s 150.091us 1 1 100.00
edn_same_csr_outstanding 1.310s 16.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.170s 52.135us 1 1 100.00
edn_csr_rw 1.130s 13.899us 1 1 100.00
edn_csr_aliasing 1.830s 150.091us 1 1 100.00
edn_same_csr_outstanding 1.310s 16.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.050s 617.673us 1 1 100.00
edn_tl_intg_err 1.980s 301.989us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.100s 47.099us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.510s 60.808us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.050s 617.673us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.050s 617.673us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.050s 617.673us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.050s 617.673us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.510s 60.808us 1 1 100.00
edn_sec_cm 5.050s 617.673us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.510s 60.808us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.980s 301.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 37.210s 3210.345us 1 1 100.00