Simulation Results: entropy_src/rng_16bits

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 68.25 %
  • code
  • 82.06 %
  • assert
  • 74.20 %
  • func
  • 48.49 %
  • block
  • 94.02 %
  • line
  • 97.77 %
  • branch
  • 85.86 %
  • toggle
  • 51.90 %
  • FSM
  • 92.71 %
Validation stages
V1
83.33%
V2
93.75%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 90.316us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 31.259us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 104.104us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 25.000s 4154.353us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 8.000s 205.649us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 13.938us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 104.104us 1 1 100.00
entropy_src_csr_aliasing 8.000s 205.649us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 90.316us 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
entropy_src_fw_ov 465.000s 13018.544us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 465.000s 13018.544us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
rng_max_rate 0 1 0.00
entropy_src_rng_max_rate 221.000s 5032.305us 0 1 0.00
health_checks 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
entropy_src_intr 33.000s 831.932us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
entropy_src_functional_alerts 9.000s 2016.034us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 139.000s 15055.308us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 105.858us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 21.000s 266.431us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 87.438us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 3.000s 44.096us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 9.000s 193.249us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 9.000s 193.249us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 31.259us 1 1 100.00
entropy_src_csr_rw 2.000s 104.104us 1 1 100.00
entropy_src_csr_aliasing 8.000s 205.649us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 29.885us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 31.259us 1 1 100.00
entropy_src_csr_rw 2.000s 104.104us 1 1 100.00
entropy_src_csr_aliasing 8.000s 205.649us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 29.885us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 179.085us 1 1 100.00
entropy_src_tl_intg_err 6.000s 606.602us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
entropy_src_cfg_regwen 3.000s 52.402us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
entropy_src_fw_ov 465.000s 13018.544us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 105.858us 1 1 100.00
entropy_src_sec_cm 3.000s 179.085us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 105.858us 1 1 100.00
entropy_src_sec_cm 3.000s 179.085us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 71.000s 14764.010us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 105.858us 1 1 100.00
entropy_src_sec_cm 3.000s 179.085us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 105.858us 1 1 100.00
entropy_src_sec_cm 3.000s 179.085us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 105.858us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 9.000s 2016.034us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 6.000s 606.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 124.000s 14069.048us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 30.000s 852.807us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:2940) [scoreboard] Check failed prediction == csr_val (* [*] vs * [*]) Prediction for observe FIFO access failed. 1 test run
entropy_src_rng_max_rate 105917040964592960189455144602305002343468554451794868028660651485517742914422 1214
UVM_INFO @ 5032304663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 67602429096311710144735207060225459615713867611694968353042719879183678453062 125
UVM_INFO @ 852806858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_hi_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 37394847693160123694841591692900959821282651362597681965348714389091444706302 113
UVM_INFO @ 13938305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---