Simulation Results: hmac

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.77 %
  • code
  • 83.23 %
  • assert
  • 97.17 %
  • func
  • 28.92 %
  • block
  • 97.51 %
  • line
  • 98.44 %
  • branch
  • 93.76 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 11.000s 1224.137us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.000s 54.812us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 119.502us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 325.739us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 1337.118us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.000s 77.882us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 119.502us 1 1 100.00
hmac_csr_aliasing 6.000s 1337.118us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 41.000s 1576.952us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 123.000s 9713.959us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 15.000s 914.095us 1 1 100.00
hmac_test_sha384_vectors 520.000s 48043.539us 1 1 100.00
hmac_test_sha512_vectors 34.000s 310.633us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 477.652us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 548.071us 1 1 100.00
hmac_test_hmac512_vectors 23.000s 1915.245us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 24.000s 513.574us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 84.000s 6659.756us 1 1 100.00
error 1 1 100.00
hmac_error 10.000s 3302.522us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 36.000s 1738.853us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 11.000s 1224.137us 1 1 100.00
hmac_long_msg 41.000s 1576.952us 1 1 100.00
hmac_back_pressure 123.000s 9713.959us 1 1 100.00
hmac_datapath_stress 84.000s 6659.756us 1 1 100.00
hmac_burst_wr 24.000s 513.574us 1 1 100.00
hmac_stress_all 91.000s 27011.032us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 11.000s 1224.137us 1 1 100.00
hmac_long_msg 41.000s 1576.952us 1 1 100.00
hmac_back_pressure 123.000s 9713.959us 1 1 100.00
hmac_datapath_stress 84.000s 6659.756us 1 1 100.00
hmac_wipe_secret 36.000s 1738.853us 1 1 100.00
hmac_test_sha256_vectors 15.000s 914.095us 1 1 100.00
hmac_test_sha384_vectors 520.000s 48043.539us 1 1 100.00
hmac_test_sha512_vectors 34.000s 310.633us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 477.652us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 548.071us 1 1 100.00
hmac_test_hmac512_vectors 23.000s 1915.245us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 11.000s 1224.137us 1 1 100.00
hmac_long_msg 41.000s 1576.952us 1 1 100.00
hmac_back_pressure 123.000s 9713.959us 1 1 100.00
hmac_datapath_stress 84.000s 6659.756us 1 1 100.00
hmac_burst_wr 24.000s 513.574us 1 1 100.00
hmac_error 10.000s 3302.522us 1 1 100.00
hmac_wipe_secret 36.000s 1738.853us 1 1 100.00
hmac_test_sha256_vectors 15.000s 914.095us 1 1 100.00
hmac_test_sha384_vectors 520.000s 48043.539us 1 1 100.00
hmac_test_sha512_vectors 34.000s 310.633us 1 1 100.00
hmac_test_hmac256_vectors 19.000s 477.652us 1 1 100.00
hmac_test_hmac384_vectors 17.000s 548.071us 1 1 100.00
hmac_test_hmac512_vectors 23.000s 1915.245us 1 1 100.00
hmac_stress_all 91.000s 27011.032us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 91.000s 27011.032us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 11.872us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 2.000s 16.206us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 5.000s 276.195us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 5.000s 276.195us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.000s 54.812us 1 1 100.00
hmac_csr_rw 2.000s 119.502us 1 1 100.00
hmac_csr_aliasing 6.000s 1337.118us 1 1 100.00
hmac_same_csr_outstanding 2.000s 62.247us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.000s 54.812us 1 1 100.00
hmac_csr_rw 2.000s 119.502us 1 1 100.00
hmac_csr_aliasing 6.000s 1337.118us 1 1 100.00
hmac_same_csr_outstanding 2.000s 62.247us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 353.875us 1 1 100.00
hmac_tl_intg_err 4.000s 355.316us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 355.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 11.000s 1224.137us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 116.301us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 104.000s 5520.373us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 35.628us 1 1 100.00