Simulation Results

Simulation Results: i2c

24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.49 %

code
85.68 %

assert
97.25 %

func
82.54 %

block
95.95 %

line
95.29 %

branch
92.73 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		82.93%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	27.000s	1326.031us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	17.000s	3048.702us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	2.000s	24.912us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	21.831us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	7.000s	2665.637us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	3.000s	394.240us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	62.101us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	21.831us	1	1	100.00
	i2c_csr_aliasing	3.000s	394.240us	1	1	100.00

34/41 passed

82.93 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	3.000s	69.199us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	327.000s	10844.387us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	47.000s	6763.678us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	31.821us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3601.000s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	1986.000s	2088.970us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	144.976us	1	1	100.00
	i2c_host_fifo_fmt_empty	93.000s	1671.577us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	132.149us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	1324.000s	12819.727us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.000s	945.519us	1	1	100.00
i2c_host_mode_toggle				1	1	100.00
	i2c_host_mode_toggle	5.000s	500.053us	1	1	100.00
target_glitch				0	1	0.00
	i2c_target_glitch	3.000s	1594.735us	0	1	0.00
target_stress_all				0	1	0.00
	i2c_target_stress_all	3600.000s	0.000us	0	1	0.00
target_maxperf				1	1	100.00
	i2c_target_perf	7.000s	1029.651us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	34.000s	8171.199us	1	1	100.00
	i2c_target_intr_smoke	6.000s	2095.061us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	1244.916us	1	1	100.00
	i2c_target_fifo_reset_tx	2.000s	138.600us	1	1	100.00
target_fifo_full				2	3	66.67
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	34.000s	8171.199us	1	1	100.00
	i2c_target_intr_stress_wr	2722.000s	41759.317us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	8.000s	4353.024us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	9.000s	1743.520us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	6.000s	2446.762us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	50.000s	10112.952us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	3.000s	986.585us	1	1	100.00
	i2c_target_fifo_watermarks_tx	2.000s	364.005us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	47.000s	6763.678us	1	1	100.00
	i2c_host_perf_precise	12.000s	1218.960us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.000s	945.519us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.000s	102.911us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	4.000s	6313.424us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	781.877us	1	1	100.00
	i2c_target_nack_txstretch	3.000s	161.083us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.000s	1036.608us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	1679.680us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	42.546us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	2.000s	37.857us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	634.865us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	634.865us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	24.912us	1	1	100.00
	i2c_csr_rw	2.000s	21.831us	1	1	100.00
	i2c_csr_aliasing	3.000s	394.240us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	89.196us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	2.000s	24.912us	1	1	100.00
	i2c_csr_rw	2.000s	21.831us	1	1	100.00
	i2c_csr_aliasing	3.000s	394.240us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	89.196us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	246.515us	1	1	100.00
	i2c_sec_cm	2.000s	194.719us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	246.515us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	6.000s	118.141us	1
target_error_intr				1
	i2c_target_unexp_stop	2.000s	285.589us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.000s	2065.776us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	99724528640532043766963497055886782941822778758179616772904782569757297378526	None
	i2c_target_stress_wr	1406285274724176498014043865352241313211640142650273310254618851777911647951	None
	i2c_target_stress_all	10132115334696336886367231695739536194195482932815791201722958228126172317964	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	21384534618090877579787392279247433206308992161266903898236196436293208605642	97	UVM_INFO @ 69198653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	101467169714614415005830208525868000780552008963286124343780410040454791587726	157	UVM_INFO @ 10844387044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	58411099412914592673441562427809878401353583231793989475772450850147694173637	113	UVM_INFO @ 118141300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	39141311801502266263980758238083619990959482044549157493431237248658111685699	94	UVM_INFO @ 2065776413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	11733857814875642672733589681017799459691021841103145335080998790784786759527	93	UVM_INFO @ 1594734810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	27899467110951169243254586448745149266294506951049414935439891544843799646137	87	UVM_INFO @ 285589180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	1546037649034259072445333975067428614796480547669663672951754550452805122906	88	UVM_INFO @ 10112952374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---