Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.81 %
  • code
  • 88.96 %
  • assert
  • 96.40 %
  • func
  • 78.06 %
  • block
  • 95.85 %
  • line
  • 96.81 %
  • branch
  • 89.43 %
  • toggle
  • 79.13 %
  • FSM
  • 90.48 %
Validation stages
V1
100.00%
V2
70.00%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 36.582us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 60.034us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 2.000s 33.947us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 24.823us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 170.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 18.374us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 2.000s 33.947us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 170.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 356.315us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 116.638us 1 1 100.00
lc_prog_failure 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 1 7 14.29
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 6.000s 330.681us 1 1 100.00
lc_ctrl_jtag_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
jtag_access 10 13 76.92
lc_ctrl_jtag_smoke 3.000s 638.853us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 7.000s 743.581us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 1203.383us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 277.205us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 133.701us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 3904.695us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.000s 1089.118us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 51.139us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.000s 101.467us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 563.737us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.000s 802.921us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 14.681us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10802.113s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 24.668us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 87.296us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 87.296us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 60.034us 1 1 100.00
lc_ctrl_csr_rw 2.000s 33.947us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 170.140us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 167.968us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 60.034us 1 1 100.00
lc_ctrl_csr_rw 2.000s 33.947us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 170.140us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 167.968us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 200.887us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 200.887us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.000s 356.315us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 3.000s 1717.039us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.000s 330.681us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3601.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.000s 387.435us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 612.362us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 612.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 11 test runs
lc_ctrl_state_failure 44794924452534007278998137547562201439385437285793940196230481677448366345335 None
lc_ctrl_state_post_trans 109250293481602113961212329507197630797015923736413765619505929164499370025712 None
lc_ctrl_prog_failure 83070951181475447781032606853460897831553191628101043562114936360823662340848 None
lc_ctrl_errors 90241844269387553548894538036284585061299662835456043844038935064744007936892 None
lc_ctrl_jtag_state_failure 80129676068202854945669197708798364918984581423830917997361850781660362815617 None
lc_ctrl_jtag_state_post_trans 55372834942682736269073791842605955994253717676815723880003658825069150995145 None
lc_ctrl_jtag_prog_failure 86367617945988229426542658495492501433358587661938225841896190292255583725782 None
lc_ctrl_jtag_errors 40404136367545998093623492576689392512843226117476736776540806737957574572751 None
lc_ctrl_sec_mubi 5404654987119386899165602247421360977859572436991088309995423141535512337473 None
lc_ctrl_stress_all 72202447503242531946608368009398755616683990428929765346921866319583770069198 None
lc_ctrl_stress_all_with_rand_reset 33577686087318828059014749558036312061306360204002063013638324806289527977306 None