Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.68 %
  • code
  • 90.62 %
  • assert
  • 95.97 %
  • func
  • 76.45 %
  • block
  • 96.34 %
  • line
  • 97.21 %
  • branch
  • 90.73 %
  • toggle
  • 79.31 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
76.67%
V2S
60.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.000s 17.072us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 18.528us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.000s 64.503us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 55.033us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 28.603us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 115.102us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.000s 64.503us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 28.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 1 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1346.031us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 2.000s 37.011us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.000s 70.651us 1 1 100.00
lc_state_failure 0 1 0.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_errors 0 1 0.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
security_escalation 3 7 42.86
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_prog_failure 2.000s 70.651us 1 1 100.00
lc_ctrl_errors 3600.000s 0.000us 0 1 0.00
lc_ctrl_security_escalation 5.000s 322.237us 1 1 100.00
lc_ctrl_jtag_state_failure 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 68.751us 1 1 100.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
jtag_access 11 13 84.62
lc_ctrl_jtag_smoke 4.000s 253.452us 1 1 100.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_prog_failure 3.000s 68.751us 1 1 100.00
lc_ctrl_jtag_errors 3601.000s 0.000us 0 1 0.00
lc_ctrl_jtag_access 2.000s 58.915us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 2485.796us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.000s 64.571us 1 1 100.00
lc_ctrl_jtag_csr_rw 3.000s 38.253us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.000s 8422.409us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 363.830us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 115.871us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 1692.256us 1 1 100.00
lc_ctrl_jtag_alert_test 2.000s 327.096us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.000s 2124.155us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.000s 22.189us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 10804.478s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 2.000s 44.290us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 76.286us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 76.286us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 18.528us 1 1 100.00
lc_ctrl_csr_rw 1.000s 64.503us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 28.603us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 52.923us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 2.000s 18.528us 1 1 100.00
lc_ctrl_csr_rw 1.000s 64.503us 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 28.603us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 52.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 239.082us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.000s 239.082us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.000s 1346.031us 1 1 100.00
sec_cm_manuf_state_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_transition_ctr_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_state_config_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_main_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_kmac_fsm_sparse 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_main_fsm_local_esc 1 2 50.00
lc_ctrl_state_failure 3601.000s 0.000us 0 1 0.00
lc_ctrl_sec_cm 4.000s 241.840us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.000s 322.237us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 0 2 0.00
lc_ctrl_state_post_trans 3600.000s 0.000us 0 1 0.00
lc_ctrl_jtag_state_post_trans 3600.000s 0.000us 0 1 0.00
sec_cm_intersig_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_valid_ctrl_mubi 0 1 0.00
lc_ctrl_sec_mubi 3600.000s 0.000us 0 1 0.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.000s 2718.009us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1750.129us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.000s 1750.129us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job timed out after * minutes 9 test runs
lc_ctrl_state_failure 64084264188060228978789406719614604509740111554950361244170682274890403389401 None
lc_ctrl_state_post_trans 55463641783473067416445454323376594117513697379655921313637272520764546335991 None
lc_ctrl_errors 16045663479481856673719110897774773622910869720449789059305160179751147954682 None
lc_ctrl_jtag_state_failure 90104744544886508409515957718285292125872356117382589261434716078222627154427 None
lc_ctrl_jtag_state_post_trans 1164696626849631055173532456014159654363332685705065943929362136139547604929 None
lc_ctrl_jtag_errors 74920180752038795098979074624400052099126875160365997494055848713656725359500 None
lc_ctrl_sec_mubi 104722407110008748317626948893674790715959514323655714546793220025841743794585 None
lc_ctrl_stress_all 69338044425998044339013260233439038517228752953831177793538623947749476558282 None
lc_ctrl_stress_all_with_rand_reset 94363650281194772802066457830087495046831296085419189290660684175906038893397 None