Simulation Results: mbx

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 88.15 %
  • code
  • 89.40 %
  • assert
  • 97.43 %
  • func
  • 77.63 %
  • block
  • 96.88 %
  • line
  • 96.71 %
  • branch
  • 91.89 %
  • toggle
  • 79.59 %
Validation stages
V1
83.33%
V2
90.91%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 1 1 100.00
mbx_smoke 117.000s 9236.739us 1 1 100.00
csr_hw_reset 1 1 100.00
mbx_csr_hw_reset 2.000s 50.209us 1 1 100.00
csr_rw 1 1 100.00
mbx_csr_rw 2.000s 15.077us 1 1 100.00
csr_bit_bash 1 1 100.00
mbx_csr_bit_bash 2.000s 67.500us 1 1 100.00
csr_aliasing 1 1 100.00
mbx_csr_aliasing 2.000s 23.060us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
mbx_csr_mem_rw_with_rand_reset 2.000s 3.987us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
mbx_csr_rw 2.000s 15.077us 1 1 100.00
mbx_csr_aliasing 2.000s 23.060us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 1 1 100.00
mbx_stress 123.000s 36892.402us 1 1 100.00
mbx_max_activity 1 1 100.00
mbx_stress_zero_delays 123.000s 73056.386us 1 1 100.00
mbx_imbx_oob 1 1 100.00
mbx_imbx_oob 10.000s 405.209us 1 1 100.00
mbx_doe_intr_msg 1 1 100.00
mbx_doe_intr_msg 10.000s 3188.636us 1 1 100.00
alert_test 1 1 100.00
mbx_alert_test 2.000s 18.300us 1 1 100.00
intr_test 1 1 100.00
mbx_intr_test 2.000s 55.796us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
mbx_tl_errors 2.000s 2.762us 0 1 0.00
tl_d_illegal_access 0 1 0.00
mbx_tl_errors 2.000s 2.762us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
mbx_csr_hw_reset 2.000s 50.209us 1 1 100.00
mbx_csr_rw 2.000s 15.077us 1 1 100.00
mbx_csr_aliasing 2.000s 23.060us 1 1 100.00
mbx_same_csr_outstanding 1.000s 21.273us 1 1 100.00
tl_d_partial_access 4 4 100.00
mbx_csr_hw_reset 2.000s 50.209us 1 1 100.00
mbx_csr_rw 2.000s 15.077us 1 1 100.00
mbx_csr_aliasing 2.000s 23.060us 1 1 100.00
mbx_same_csr_outstanding 1.000s 21.273us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
mbx_tl_intg_err 3.000s 159.130us 1 1 100.00
mbx_sec_cm 1.000s 22.538us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:696) scoreboard [scoreboard] On interface mbx_soc_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
mbx_tl_errors 47802076325837089564003525438101662884672120907412597384276282436398416960387 85
TL item was: req: (cip_tl_seq_item@17323) { a_addr: 'h2270fb94 a_data: 'h753359ee a_mask: 'h0 a_size: 'h1 a_param: 'h0 a_source: 'h96 a_opcode: 'h1 a_user: 'h24c8c d_param: 'h0 d_source: 'h96 d_data: 'h0 d_size: 'h1 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h10aa a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 2762361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
mbx_csr_mem_rw_with_rand_reset 36545011854839743255844198258545145020342166583605409521025084459548790720528 86
TL item was: req: (cip_tl_seq_item@19281) { a_addr: 'h1431ff70 a_data: 'h9a4b19d2 a_mask: 'h1 a_size: 'h0 a_param: 'h0 a_source: 'h7b a_opcode: 'h1 a_user: 'h25333 d_param: 'h0 d_source: 'h7b d_data: 'h0 d_size: 'h0 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h152a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Unsupported partial write"}.
UVM_INFO @ 3986563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---