Simulation Results: otbn

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 89.67 %
  • code
  • 81.85 %
  • assert
  • 89.69 %
  • func
  • 97.46 %
  • block
  • 97.73 %
  • line
  • 97.94 %
  • branch
  • 81.82 %
  • toggle
  • 81.43 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
96.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 13.000s 219.422us 1 1 100.00
otbn_smoke_vectorized 10.000s 38.353us 1 1 100.00
single_binary 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 6.000s 23.733us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 5.000s 39.593us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 11.000s 163.075us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 5.000s 59.046us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 11.000s 50.686us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 5.000s 39.593us 1 1 100.00
otbn_csr_aliasing 5.000s 59.046us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 163.000s 5693.754us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 61.000s 4898.523us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 55.000s 386.002us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 72.000s 723.886us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 87.000s 478.405us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 19.000s 304.915us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 11.000s 90.918us 1 1 100.00
zero_state_err_urnd 0 1 0.00
otbn_zero_state_err_urnd 9.000s 36.178us 0 1 0.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 20.134us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 6.000s 78.616us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 5.000s 17.019us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 7.000s 216.569us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 7.000s 216.569us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 6.000s 23.733us 1 1 100.00
otbn_csr_rw 5.000s 39.593us 1 1 100.00
otbn_csr_aliasing 5.000s 59.046us 1 1 100.00
otbn_same_csr_outstanding 5.000s 99.779us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 6.000s 23.733us 1 1 100.00
otbn_csr_rw 5.000s 39.593us 1 1 100.00
otbn_csr_aliasing 5.000s 59.046us 1 1 100.00
otbn_same_csr_outstanding 5.000s 99.779us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 19.000s 35.811us 1 1 100.00
otbn_dmem_err 10.000s 25.028us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 11.000s 42.149us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 45.304us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 236.775us 1 1 100.00
otbn_urnd_err 8.000s 17.505us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 16.000s 44.764us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 14.000s 44.174us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 20.389us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
otbn_tl_intg_err 15.000s 1085.744us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 62.000s 193.568us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 13.000s 219.422us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 10.000s 25.028us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 19.000s 35.811us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 15.000s 1085.744us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 90.918us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 19.000s 35.811us 1 1 100.00
otbn_dmem_err 10.000s 25.028us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 36.178us 0 1 0.00
otbn_illegal_mem_acc 16.000s 44.764us 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 19.000s 35.811us 1 1 100.00
otbn_dmem_err 10.000s 25.028us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 36.178us 0 1 0.00
otbn_illegal_mem_acc 16.000s 44.764us 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 11.000s 90.918us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 19.000s 35.811us 1 1 100.00
otbn_dmem_err 10.000s 25.028us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 36.178us 0 1 0.00
otbn_illegal_mem_acc 16.000s 44.764us 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 12.000s 27.513us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 9.000s 37.989us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 33.000s 216.616us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 33.000s 216.616us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 15.000s 91.615us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 15.000s 241.744us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 80.202us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 80.202us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 13.000s 67.888us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 87.000s 478.405us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 22.961us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 14.000s 48.747us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 240.000s 2993.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 284.000s 2486.635us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_zero_state_err_urnd 51247784412289518610555229859394518501273489440677986206824640359228774285673 107
UVM_ERROR @ 36178102 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 36178102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---