Simulation Results: rv_dm/use_dmi_interface

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.43 %
  • code
  • 74.12 %
  • assert
  • 96.43 %
  • func
  • 91.74 %
  • block
  • 90.19 %
  • line
  • 89.98 %
  • branch
  • 73.39 %
  • toggle
  • 72.42 %
  • FSM
  • 60.71 %
Validation stages
V1
92.59%
V2
69.57%
V2S
71.43%
V3
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 55.000s 4978.427us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 44.000s 624.442us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 51.000s 940.196us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 55.000s 16999.372us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 39.000s 308.724us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 54.000s 5166.108us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 56.000s 3203.193us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 42.000s 9803.751us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 125.000s 46938.193us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 52.000s 297.704us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 53.000s 205.442us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 51.000s 231.525us 1 1 100.00
mem_tl_access_resuming 0 1 0.00
rv_dm_mem_tl_access_resuming 38.000s 127.319us 0 1 0.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 52.000s 290.472us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 41.000s 1600.637us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 39.000s 217.888us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 44.000s 1259.115us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 52.000s 297.704us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 39.000s 324.556us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 36.000s 278.110us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 51.000s 231.525us 1 1 100.00
rom_read_access 0 1 0.00
rv_dm_rom_read_access 45.000s 113.942us 0 1 0.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 46.000s 324.478us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 41.000s 135.559us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 62.000s 4426.390us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 68.000s 671.364us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_dm_csr_mem_rw_with_rand_reset 50.000s 95.807us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 68.000s 671.364us 1 1 100.00
rv_dm_csr_rw 41.000s 135.559us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 38.000s 95.550us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 48.000s 127.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 55.000s 4978.427us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 48.000s 356.473us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 51.000s 319.464us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 34.000s 143.671us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 50.000s 368.945us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 46.000s 6699.409us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 47.000s 86.547us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 48.000s 5928.930us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 44.000s 1126.828us 0 1 0.00
jtag_dmi_debug_disabled 0 1 0.00
rv_dm_jtag_dmi_debug_disabled 45.000s 449.094us 0 1 0.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 38.000s 4881.817us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 40.000s 507.749us 1 1 100.00
hart_unavail 0 1 0.00
rv_dm_hart_unavail 50.000s 35.875us 0 1 0.00
tap_ctrl_transitions 2 2 100.00
rv_dm_tap_fsm 54.000s 7994.444us 1 1 100.00
rv_dm_tap_fsm_rand_reset 75.000s 9248.629us 1 1 100.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 42.000s 57.710us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 46.000s 348.461us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 38.000s 54.285us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_dm_tl_errors 51.000s 339.573us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_dm_tl_errors 51.000s 339.573us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 68.000s 671.364us 1 1 100.00
rv_dm_csr_hw_reset 46.000s 324.478us 1 1 100.00
rv_dm_csr_rw 41.000s 135.559us 1 1 100.00
rv_dm_same_csr_outstanding 54.000s 579.688us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 68.000s 671.364us 1 1 100.00
rv_dm_csr_hw_reset 46.000s 324.478us 1 1 100.00
rv_dm_csr_rw 41.000s 135.559us 1 1 100.00
rv_dm_same_csr_outstanding 54.000s 579.688us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
rv_dm_sec_cm 48.000s 34.954us 0 1 0.00
rv_dm_tl_intg_err 46.000s 3499.716us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 46.000s 3499.716us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 38.000s 4881.817us 1 1 100.00
rv_dm_debug_disabled 35.000s 40.272us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 38.000s 4881.817us 1 1 100.00
rv_dm_debug_disabled 35.000s 40.272us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 55.000s 4978.427us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 0 1 0.00
rv_dm_buffered_enable 39.000s 133.935us 0 1 0.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 51.000s 86.001us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 51.000s 86.001us 1 1 100.00
sec_cm_exec_ctrl_mubi 0 1 0.00
rv_dm_buffered_enable 39.000s 133.935us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rv_dm_stress_all_with_rand_reset 75.000s 2900.389us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
rv_dm_scanmode 95.000s 300000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_dm_scoreboard.sv:480) [scoreboard] sba_tl_access_q item uncompared: 2 test runs
rv_dm_sba_tl_access 66150326599790228257853956970122959577811849163019766341482723616870729288414 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23809
rv_dm_bad_sba_tl_access 67763927667639823349873929589637915320598745387923059728477821047116890066557 87
-------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------
req cip_tl_seq_item - @23926
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp 2 test runs
rv_dm_delayed_resp_sba_tl_access 97526181429133361412127637766205916807922594537787184558621295560170737634704 107
UVM_INFO @ 86547065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_autoincr_sba_tl_access 91633309076649329645737843161639012761812621482519280749981713064534495326971 107
UVM_INFO @ 1126828369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [*] vs * [*]) 2 test runs
rv_dm_hart_unavail 32538754813284979337775464816446339396477373626343320678104048163140906064114 87
UVM_INFO @ 35875173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_dm_stress_all 63295843173361469560876436249620441454681052088263262439251977206202484806843 88
UVM_INFO @ 348460688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == *'b* (* [*] vs * [*]) 1 test run
rv_dm_mem_tl_access_resuming 35429599344626589501526343670645409981744516212809404066493862591738936378258 87
UVM_INFO @ 127319154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) 1 test run
rv_dm_jtag_dmi_debug_disabled 91565455276462021897392365284894685994045413019962885316592311432849755284858 87
UVM_INFO @ 449094372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=*, but it was *"}. Item: (req: (cip_tl_seq_item@23869) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } 1 test run
rv_dm_rom_read_access 88152059222000216913672903794442591109429632248416371040772374593934385299057 87
).
UVM_INFO @ 113941727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [*] vs * [*]) 1 test run
rv_dm_buffered_enable 25996358509317509303409270815712423059701313305400960095013490607076743261518 91
UVM_INFO @ 133935340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rv_dm_scanmode 35091699975727997357006842583304322003289041404256227147438866168954507975179 87
UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rv_dm_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
rv_dm_sec_cm 79318488243748298064240990183448566141209805343934119039553935950163213871621 92
UVM_INFO @ 34953649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---