Simulation Results: spi_device/1r1w

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.73 %
  • code
  • 89.50 %
  • assert
  • 95.40 %
  • func
  • 69.30 %
  • block
  • 98.32 %
  • line
  • 98.74 %
  • branch
  • 96.95 %
  • toggle
  • 72.75 %
  • FSM
  • 89.58 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 68.000s 2353.114us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 3.000s 298.083us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.000s 71.068us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 42.000s 798.642us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 9.000s 352.345us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.000s 202.827us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.000s 71.068us 1 1 100.00
spi_device_csr_aliasing 9.000s 352.345us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 2.000s 32.650us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 3.000s 56.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 2.000s 15.762us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 2.000s 9.920us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 2.000s 4.390us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.000s 154.346us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.000s 154.346us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 8.000s 2271.536us 1 1 100.00
spi_device_tpm_sts_read 2.000s 66.974us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 18.000s 2411.119us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 24.000s 2532.165us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.000s 251.657us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.000s 251.657us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 17.000s 1978.532us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 17.000s 1978.532us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 17.000s 1978.532us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 17.000s 1978.532us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 17.000s 1978.532us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 8.000s 283.448us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 225.000s 19899.167us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 225.000s 19899.167us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 225.000s 19899.167us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 13.000s 1313.358us 1 1 100.00
spi_device_read_buffer_direct 16.000s 2632.433us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 225.000s 19899.167us 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 37.000s 1115.052us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.000s 53.053us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.000s 53.053us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 77.000s 7922.051us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 68.000s 2353.114us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 151.000s 33792.787us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 600.000s 39329.195us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 1.000s 44.863us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 2.000s 16.853us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.000s 123.164us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.000s 123.164us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 298.083us 1 1 100.00
spi_device_csr_rw 2.000s 71.068us 1 1 100.00
spi_device_csr_aliasing 9.000s 352.345us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 130.771us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 3.000s 298.083us 1 1 100.00
spi_device_csr_rw 2.000s 71.068us 1 1 100.00
spi_device_csr_aliasing 9.000s 352.345us 1 1 100.00
spi_device_same_csr_outstanding 5.000s 130.771us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 3.000s 115.935us 1 1 100.00
spi_device_tl_intg_err 7.000s 457.180us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 7.000s 457.180us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ1] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice) 1 test run
spi_device_mem_parity 23731968316253747282095283089943376374164200240273438276430832962328512566171 87
UVM_ERROR @ 7319499 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
ERROR: VHPI NOTFOUND
Name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947] not found within the scope .
UVM_ERROR @ 7319499 ps: (uvm_hdl_inca.c:743) [UVM/DPI/NOBJ2] name tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[947] cannot be resolved to a hdl object (vlog,vhdl,vlog-slice)
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 82463731381961450076756611592934146812128133274180149653390293414140060972959 85
UVM_ERROR @ 1705893 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x11b [100011011] vs 0x0 [0])
UVM_ERROR @ 1788893 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb9 [10111001] vs 0x0 [0])
UVM_ERROR @ 1875893 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2b2 [1010110010] vs 0x0 [0])
UVM_ERROR @ 1882893 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x143 [101000011] vs 0x0 [0])