Simulation Results: spi_host

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 91.74 %
  • code
  • 91.30 %
  • assert
  • 95.27 %
  • func
  • 88.66 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 67.000s 6447.843us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 41.368us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 15.494us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 153.620us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 152.379us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 65.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 15.494us 1 1 100.00
spi_host_csr_aliasing 1.000s 152.379us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.283us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 25.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 22.663us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 4.000s 233.225us 1 1 100.00
spi_host_error_cmd 2.000s 20.803us 1 1 100.00
spi_host_event 168.000s 15744.814us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 3.000s 111.504us 1 1 100.00
speed 1 1 100.00
spi_host_speed 3.000s 111.504us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 3.000s 111.504us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 406.000s 76106.160us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 129.806us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 88.795us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 3.000s 111.504us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 3.000s 111.504us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 67.000s 6447.843us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 67.000s 6447.843us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 448.984us 1 1 100.00
spien 1 1 100.00
spi_host_spien 3.000s 523.685us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 30.000s 925.482us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 101.148us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 4.000s 233.225us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 26.489us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 179.168us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 101.924us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 101.924us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 41.368us 1 1 100.00
spi_host_csr_rw 1.000s 15.494us 1 1 100.00
spi_host_csr_aliasing 1.000s 152.379us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 19.063us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 41.368us 1 1 100.00
spi_host_csr_rw 1.000s 15.494us 1 1 100.00
spi_host_csr_aliasing 1.000s 152.379us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 19.063us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 159.469us 1 1 100.00
spi_host_sec_cm 1.000s 193.437us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 159.469us 1 1 100.00