Simulation Results: sram_ctrl/main

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 95.16 %
  • code
  • 93.69 %
  • assert
  • 97.83 %
  • func
  • 93.96 %
  • block
  • 92.66 %
  • line
  • 93.64 %
  • branch
  • 89.29 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 645.431us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 41.438us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.559us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 110.136us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.666us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 361.787us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.559us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.666us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 274.000s 45417.002us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 131.000s 20247.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 4.000s 1828.024us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 99.000s 2652.242us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 221.000s 32913.668us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 60.000s 8667.566us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 89.000s 44194.120us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 95.000s 44944.120us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1361.612us 1 1 100.00
sram_ctrl_partial_access_b2b 260.000s 38621.079us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 5.000s 3312.172us 1 1 100.00
sram_ctrl_throughput_w_partial_write 5.000s 1338.030us 1 1 100.00
sram_ctrl_throughput_w_readback 5.000s 1352.802us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 17.000s 4624.892us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 356.522us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 62.000s 19278.769us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 40.005us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 28.688us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 28.688us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 41.438us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.559us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.666us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 66.267us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 41.438us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.559us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 39.666us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 66.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 15447.013us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 407.147us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1972.691us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 407.147us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 1972.691us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 17.000s 4624.892us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 17.000s 4624.892us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.559us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 95.000s 44944.120us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 95.000s 44944.120us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 95.000s 44944.120us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 89.000s 44194.120us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 19.000s 15447.013us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 645.431us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 645.431us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 95.000s 44944.120us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 407.147us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 89.000s 44194.120us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 407.147us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 407.147us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 645.431us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 407.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 61.000s 1954.771us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 44371556561557665146131593218296642743243633103204145797384216841682741618168 None
sram_ctrl_mubi_enc_err 94353950489307514061777414745671930984920909086576045736001983641826242337772 None