Simulation Results: sram_ctrl/ret

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 90.74 %
  • code
  • 81.75 %
  • assert
  • 98.08 %
  • func
  • 92.40 %
  • block
  • 92.19 %
  • line
  • 93.78 %
  • branch
  • 88.23 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 387.302us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 35.162us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.954us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 61.402us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 26.677us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 33.171us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.954us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 26.677us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 419.385us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 225.249us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 734.655us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 183.000s 2886.577us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 9.000s 483.431us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 29.000s 1585.594us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 861.461us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 12.000s 1688.927us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 142.964us 1 1 100.00
sram_ctrl_partial_access_b2b 161.000s 7109.614us 1 1 100.00
max_throughput 3 3 100.00
sram_ctrl_max_throughput 2.000s 69.149us 1 1 100.00
sram_ctrl_throughput_w_partial_write 2.000s 446.990us 1 1 100.00
sram_ctrl_throughput_w_readback 2.000s 109.652us 1 1 100.00
regwen 1 1 100.00
sram_ctrl_regwen 2.000s 497.033us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 28.889us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 41.000s 18832.895us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 23.486us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 518.839us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 5.000s 518.839us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 35.162us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.954us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 26.677us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 18.469us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 35.162us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.954us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 26.677us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 18.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 5562.833us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 250.443us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 217.318us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 250.443us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 217.318us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 497.033us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 2.000s 497.033us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.954us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1688.927us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1688.927us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 12.000s 1688.927us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 861.461us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 0 1 0.00
sram_ctrl_mubi_enc_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 5562.833us 1 1 100.00
sec_cm_mem_readback 0 1 0.00
sram_ctrl_readback_err 3600.000s 0.000us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 387.302us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 387.302us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 12.000s 1688.927us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 250.443us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 861.461us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 250.443us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 250.443us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 387.302us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 250.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 54.000s 8035.011us 1 1 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 2 test runs
sram_ctrl_readback_err 96206363184202032150372645236017649141533785004830976450640995320531977938745 None
sram_ctrl_mubi_enc_err 85259272634039906326709957401888195413096635792303485704250025133306315552546 None