Simulation Results: uart

 
24/08/2026 21:37:39 DVSim: v1.51.2 sha: 4243cf5 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 93.83 %
  • code
  • 92.53 %
  • assert
  • 98.27 %
  • func
  • 90.69 %
  • block
  • 98.83 %
  • line
  • 99.24 %
  • branch
  • 97.79 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.000s 455.442us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 37.996us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 1.000s 55.012us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 5.000s 309.294us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 2.000s 48.356us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 131.490us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 1.000s 55.012us 1 1 100.00
uart_csr_aliasing 2.000s 48.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 10.000s 91767.221us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.000s 455.442us 1 1 100.00
uart_tx_rx 10.000s 91767.221us 1 1 100.00
parity_error 2 2 100.00
uart_intr 40.000s 25336.883us 1 1 100.00
uart_rx_parity_err 97.000s 57324.416us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 10.000s 91767.221us 1 1 100.00
uart_intr 40.000s 25336.883us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 24.000s 40096.512us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 37.000s 26624.108us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 35.000s 25428.949us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 40.000s 25336.883us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 40.000s 25336.883us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 40.000s 25336.883us 1 1 100.00
perf 1 1 100.00
uart_perf 119.000s 19052.335us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 16.000s 12016.535us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 16.000s 12016.535us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 18.000s 73724.895us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 6.000s 2814.372us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 37.000s 7127.150us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.000s 5159.092us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 261.000s 90552.912us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 14.000s 3434.282us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 1.000s 14.670us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 2.000s 18.398us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 2.000s 83.143us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 2.000s 83.143us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 1.000s 37.996us 1 1 100.00
uart_csr_rw 1.000s 55.012us 1 1 100.00
uart_csr_aliasing 2.000s 48.356us 1 1 100.00
uart_same_csr_outstanding 2.000s 22.047us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 1.000s 37.996us 1 1 100.00
uart_csr_rw 1.000s 55.012us 1 1 100.00
uart_csr_aliasing 2.000s 48.356us 1 1 100.00
uart_same_csr_outstanding 2.000s 22.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.000s 127.370us 1 1 100.00
uart_tl_intg_err 2.000s 342.001us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 2.000s 342.001us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 21.000s 1751.628us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_stress_all 58947269264059278880948210216021665866143457355094565297663557833851179815899 84
UVM_ERROR @ 182709217 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 182709217 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 204209905 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 8
UVM_ERROR @ 204230739 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty