Simulation Results: ac_range_check

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 82.93 %
  • code
  • 93.12 %
  • assert
  • 97.75 %
  • func
  • 57.93 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 81.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 1 1 100.00
ac_range_check_smoke 51.000s 1925.410us 1 1 100.00
ac_range_check_smoke_racl 1 1 100.00
ac_range_check_smoke_racl 55.000s 2117.785us 1 1 100.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 10.000s 39.332us 1 1 100.00
csr_rw 1 1 100.00
ac_range_check_csr_rw 10.000s 57.066us 1 1 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 39.000s 7053.144us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 12.000s 145.086us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
ac_range_check_csr_mem_rw_with_rand_reset 10.000s 72.659us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
ac_range_check_csr_rw 10.000s 57.066us 1 1 100.00
ac_range_check_csr_aliasing 12.000s 145.086us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 1 1 100.00
ac_range_check_lock_range 10.000s 61.626us 1 1 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 47.000s 10520.819us 1 1 100.00
stress_all 1 1 100.00
ac_range_check_stress_all 222.000s 8589.822us 1 1 100.00
alert_test 1 1 100.00
ac_range_check_alert_test 10.000s 16.064us 1 1 100.00
intr_test 1 1 100.00
ac_range_check_intr_test 9.000s 67.765us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
ac_range_check_tl_errors 5.000s 98.175us 1 1 100.00
tl_d_illegal_access 1 1 100.00
ac_range_check_tl_errors 5.000s 98.175us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 39.332us 1 1 100.00
ac_range_check_csr_rw 10.000s 57.066us 1 1 100.00
ac_range_check_csr_aliasing 12.000s 145.086us 1 1 100.00
ac_range_check_same_csr_outstanding 11.000s 56.121us 1 1 100.00
tl_d_partial_access 4 4 100.00
ac_range_check_csr_hw_reset 10.000s 39.332us 1 1 100.00
ac_range_check_csr_rw 10.000s 57.066us 1 1 100.00
ac_range_check_csr_aliasing 12.000s 145.086us 1 1 100.00
ac_range_check_same_csr_outstanding 11.000s 56.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 782.326us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 782.326us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 782.326us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
ac_range_check_shadow_reg_errors 17.000s 782.326us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 120.000s 18719.225us 1 1 100.00
tl_intg_err 2 2 100.00
ac_range_check_sec_cm 7.000s 66.751us 1 1 100.00
ac_range_check_tl_intg_err 9.000s 1895.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
ac_range_check_stress_all_with_rand_reset 310.000s 20240.733us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
ac_range_check_smoke_high_threshold 40.000s 2835.565us 1 1 100.00