Simulation Results: aes/gcm_masked

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 87.11 %
  • code
  • 95.14 %
  • assert
  • 98.29 %
  • func
  • 67.89 %
  • block
  • 95.77 %
  • line
  • 97.51 %
  • branch
  • 89.52 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
94.44%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 79.896us 1 1 100.00
smoke 1 1 100.00
aes_smoke 5.000s 102.487us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 57.571us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 3.000s 74.215us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 485.656us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 57.589us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 115.485us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 3.000s 74.215us 1 1 100.00
aes_csr_aliasing 2.000s 57.589us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 5.000s 102.487us 1 1 100.00
aes_config_error 4.000s 73.127us 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
key_length 3 3 100.00
aes_smoke 5.000s 102.487us 1 1 100.00
aes_config_error 4.000s 73.127us 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 95.411us 1 1 100.00
aes_b2b 15.000s 868.224us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 5.000s 102.487us 1 1 100.00
aes_config_error 4.000s 73.127us 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
aes_alert_reset 8.000s 313.931us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 111.824us 1 1 100.00
aes_config_error 4.000s 73.127us 1 1 100.00
aes_alert_reset 8.000s 313.931us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 114.365us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 11.000s 722.649us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 10.000s 952.692us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 8.000s 313.931us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 95.411us 1 1 100.00
aes_sideload 5.000s 82.048us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 104.466us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 18.000s 1641.463us 0 1 0.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 112.537us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 94.805us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 5.000s 1116.536us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 5.000s 1116.536us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.571us 1 1 100.00
aes_csr_rw 3.000s 74.215us 1 1 100.00
aes_csr_aliasing 2.000s 57.589us 1 1 100.00
aes_same_csr_outstanding 2.000s 117.927us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 57.571us 1 1 100.00
aes_csr_rw 3.000s 74.215us 1 1 100.00
aes_csr_aliasing 2.000s 57.589us 1 1 100.00
aes_same_csr_outstanding 2.000s 117.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 931.902us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 4.000s 132.026us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 10.000s 2676.892us 1 1 100.00
aes_tl_intg_err 3.000s 157.900us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 3.000s 157.900us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 8.000s 313.931us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 5.000s 102.487us 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
aes_alert_reset 8.000s 313.931us 1 1 100.00
aes_core_fi 3.000s 92.722us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 112.537us 1 1 100.00
aes_config_error 4.000s 73.127us 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
aes_core_fi 3.000s 92.722us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 124.795us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 62.237us 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 95.411us 1 1 100.00
aes_sideload 5.000s 82.048us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 62.237us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 62.237us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 62.237us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 62.237us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 62.237us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 95.411us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2952.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
aes_ctr_fi 3.000s 51.150us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2952.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2952.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_ctr_fi 3.000s 51.150us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2952.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
aes_ctr_fi 3.000s 51.150us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 8.000s 313.931us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
aes_ctr_fi 3.000s 51.150us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
aes_ctr_fi 3.000s 51.150us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_ctr_fi 3.000s 51.150us 1 1 100.00
sec_cm_ghash_fsm_local_esc 1 2 50.00
aes_ghash_fi 2.000s 107.925us 1 1 100.00
aes_fi 2952.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2952.000s 200000.000us 0 1 0.00
aes_control_fi 2.000s 66.116us 1 1 100.00
aes_cipher_fi 2.000s 49.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 14.000s 207.437us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 89388507297919129342523919820909811661509868478871397758375800730367378414426 18411173
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:782) scoreboard [scoreboard] # * 1 test run
aes_stress_all 85611024976039217681586508882852041588064846178751942632741294296524375590956 39173
TEST FAILED MESSAGES DID NOT MATCH
0 f8 4d 4d 0
1 00 00 00 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 108569800580050602932920069410493962594761137395171426729877173575178724953158 435
UVM_INFO @ 207436734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---