Simulation Results: aes/gcm_unmasked

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 84.70 %
  • code
  • 90.44 %
  • assert
  • 97.75 %
  • func
  • 65.90 %
  • block
  • 90.41 %
  • line
  • 92.41 %
  • branch
  • 82.72 %
  • toggle
  • 97.99 %
  • FSM
  • 88.65 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 82.327us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 109.877us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 92.509us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 64.298us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 1393.047us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 79.692us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 55.009us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 64.298us 1 1 100.00
aes_csr_aliasing 2.000s 79.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 109.877us 1 1 100.00
aes_config_error 2.000s 58.779us 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 109.877us 1 1 100.00
aes_config_error 2.000s 58.779us 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 105.257us 1 1 100.00
aes_b2b 7.000s 244.680us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 109.877us 1 1 100.00
aes_config_error 2.000s 58.779us 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
aes_alert_reset 4.000s 140.918us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 90.726us 1 1 100.00
aes_config_error 2.000s 58.779us 1 1 100.00
aes_alert_reset 4.000s 140.918us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 299.549us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 8.000s 1838.981us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 140.918us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 105.257us 1 1 100.00
aes_sideload 4.000s 95.797us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 261.421us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 9.000s 398.184us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 64.864us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 82.570us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 82.570us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 92.509us 1 1 100.00
aes_csr_rw 1.000s 64.298us 1 1 100.00
aes_csr_aliasing 2.000s 79.692us 1 1 100.00
aes_same_csr_outstanding 2.000s 67.263us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 92.509us 1 1 100.00
aes_csr_rw 1.000s 64.298us 1 1 100.00
aes_csr_aliasing 2.000s 79.692us 1 1 100.00
aes_same_csr_outstanding 2.000s 67.263us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 132.758us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 5.000s 199.626us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 590.823us 1 1 100.00
aes_tl_intg_err 2.000s 196.960us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 196.960us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 140.918us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 109.877us 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
aes_alert_reset 4.000s 140.918us 1 1 100.00
aes_core_fi 2.000s 224.894us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 58.779us 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
aes_core_fi 2.000s 224.894us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 150.488us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 58.259us 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 105.257us 1 1 100.00
aes_sideload 4.000s 95.797us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 58.259us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 58.259us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 58.259us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 58.259us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 58.259us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 105.257us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 1081.000s 200000.000us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
aes_ctr_fi 2.000s 49.730us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 1081.000s 200000.000us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 1081.000s 200000.000us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_ctr_fi 2.000s 49.730us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 1081.000s 200000.000us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
aes_ctr_fi 2.000s 49.730us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 140.918us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
aes_ctr_fi 2.000s 49.730us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
aes_ctr_fi 2.000s 49.730us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_ctr_fi 2.000s 49.730us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 1081.000s 200000.000us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 1081.000s 200000.000us 0 1 0.00
aes_control_fi 1.000s 50.312us 1 1 100.00
aes_cipher_fi 3.000s 56.149us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 36.095us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
aes_fi 113959167864042542036794319944934824962035697379103587999340593764202027603043 1712594
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 71285872122097307078887424089786595613335087790926720750588258975499444371864 169
UVM_INFO @ 36095227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---