Simulation Results: alert_handler

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.03 %
  • code
  • 88.04 %
  • assert
  • 97.39 %
  • func
  • 78.66 %
  • line
  • 99.52 %
  • branch
  • 98.33 %
  • cond
  • 91.71 %
  • toggle
  • 87.76 %
  • FSM
  • 62.90 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 6.440s 74.439us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 9.330s 92.432us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 7.550s 73.504us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 293.350s 14551.296us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 88.920s 3541.443us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 6.930s 70.503us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 7.550s 73.504us 1 1 100.00
alert_handler_csr_aliasing 88.920s 3541.443us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 80.670s 4916.955us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 29.190s 1034.063us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 2127.810s 149939.902us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.070s 1687.611us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 6.440s 74.439us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 68.300s 1291.495us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 32.880s 1847.513us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 136.830s 3171.708us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2755.180s 221789.269us 1 1 100.00
alert_handler_lpg_stub_clk 3150.660s 65391.836us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 2593.300s 144827.272us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 8.960s 666.297us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.850s 58.756us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 2.130s 25.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 22.890s 288.562us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 22.890s 288.562us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 9.330s 92.432us 1 1 100.00
alert_handler_csr_rw 7.550s 73.504us 1 1 100.00
alert_handler_csr_aliasing 88.920s 3541.443us 1 1 100.00
alert_handler_same_csr_outstanding 13.320s 105.983us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 9.330s 92.432us 1 1 100.00
alert_handler_csr_rw 7.550s 73.504us 1 1 100.00
alert_handler_csr_aliasing 88.920s 3541.443us 1 1 100.00
alert_handler_same_csr_outstanding 13.320s 105.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 237.030s 11633.120us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 237.030s 11633.120us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 237.030s 11633.120us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 237.030s 11633.120us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 375.860s 10007.663us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
alert_handler_tl_intg_err 2.610s 119.426us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.610s 119.426us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 237.030s 11633.120us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 6.440s 74.439us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 6.440s 74.439us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 6.440s 74.439us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 6.440s 74.439us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.070s 1687.611us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2755.180s 221789.269us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.070s 1687.611us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2127.810s 149939.902us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 2127.810s 149939.902us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 17.400s 479.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 9.600s 112.283us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:482) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 49103543076497353246992832857751389186941424076496179543400545586141056690148 102
UVM_INFO @ 3171707607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 284141477807516690857010807443972701051107884302179504866825291174711623593 168
UVM_INFO @ 666297283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1296) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 988590206332959385921762298265592628042798292203236877010697642493641763152 88
UVM_INFO @ 112283414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---