Simulation Results: clkmgr

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.71 %
  • code
  • 69.50 %
  • assert
  • 89.88 %
  • func
  • 67.75 %
  • line
  • 82.32 %
  • branch
  • 87.53 %
  • cond
  • 77.82 %
  • toggle
  • 99.81 %
  • FSM
  • 0.00 %
Validation stages
V1
50.00%
V2
61.54%
V2S
50.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.160s 22.899us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.030s 13.546us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 3.250s 167.852us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.850s 2.292us 0 1 0.00
csr_mem_rw_with_rand_reset 0 1 0.00
clkmgr_csr_mem_rw_with_rand_reset 0.990s 7.386us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 1 2 50.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
clkmgr_csr_aliasing 0.850s 2.292us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 1.510s 57.366us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.410s 66.073us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 1.450s 41.146us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.160s 22.899us 1 1 100.00
frequency 0 1 0.00
clkmgr_frequency 0.920s 5.986us 0 1 0.00
frequency_timeout 0 1 0.00
clkmgr_frequency_timeout 0.810s 4.843us 0 1 0.00
frequency_overflow 0 1 0.00
clkmgr_frequency 0.920s 5.986us 0 1 0.00
stress_all 0 1 0.00
clkmgr_stress_all 1.830s 84.903us 0 1 0.00
alert_test 1 1 100.00
clkmgr_alert_test 1.400s 39.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.510s 75.600us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.510s 75.600us 1 1 100.00
tl_d_outstanding_access 2 4 50.00
clkmgr_csr_hw_reset 1.030s 13.546us 1 1 100.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
clkmgr_csr_aliasing 0.850s 2.292us 0 1 0.00
clkmgr_same_csr_outstanding 0.920s 7.432us 0 1 0.00
tl_d_partial_access 2 4 50.00
clkmgr_csr_hw_reset 1.030s 13.546us 1 1 100.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
clkmgr_csr_aliasing 0.850s 2.292us 0 1 0.00
clkmgr_same_csr_outstanding 0.920s 7.432us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 8.480s 604.225us 1 1 100.00
clkmgr_tl_intg_err 0.960s 5.657us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.480s 107.860us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.480s 107.860us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.480s 107.860us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.480s 107.860us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.920s 3.159us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 0.960s 5.657us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 0 1 0.00
clkmgr_frequency 0.920s 5.986us 0 1 0.00
sec_cm_timeout_clk_bkgn_chk 0 1 0.00
clkmgr_frequency_timeout 0.810s 4.843us 0 1 0.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.480s 107.860us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.340s 49.220us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
sec_cm_idle_ctr_redun 1 1 100.00
clkmgr_sec_cm 8.480s 604.225us 1 1 100.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.260s 33.966us 1 1 100.00
prim_count_check 1 1 100.00
clkmgr_sec_cm 8.480s 604.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 1 0.00
clkmgr_regwen 0.960s 4.898us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
clkmgr_stress_all_with_rand_reset 7.100s 335.808us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency 60587433958207309607254506907559918288512225911124659756162758603284666465363 82
UVM_INFO @ 5986216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 47531398546746424702702366776806704126745744624223749375096207580126351231514 82
UVM_INFO @ 84903483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 2 test runs
clkmgr_frequency_timeout 102646292627374863314011769098607949265582420348988330833197838030196855749812 83
UVM_INFO @ 4842870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all_with_rand_reset 2543571528537037722881541690333018627613419365091166425726196974623424864367 143
UVM_INFO @ 335807907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * 2 test runs
clkmgr_tl_intg_err 9293640733673882498567380730067886083440852174855393167488062330853518066990 91
UVM_INFO @ 5657237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_csr_mem_rw_with_rand_reset 58265639111697172580822169917934447662384061954764899592264014112061460108483 82
UVM_INFO @ 7386365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed 1 test run
clkmgr_regwen 12425665075587574024758824562816304642172995052788646154910780406873178809583 80
UVM_INFO @ 4898303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value: * 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 69012921040681678899564873036078836697998549377806004379738192662650772307 81
UVM_INFO @ 3159470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: * Wrote clkmgr_reg_block.measure_ctrl_regwen[*]: * 1 test run
clkmgr_csr_bit_bash 897228500456151544251834452611204929503221311900654977157617874287034825529 81
UVM_INFO @ 167852148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.main_meas_ctrl_shadowed reset value: * 1 test run
clkmgr_csr_aliasing 101665151738580003049660909631371815306129335144068759911153487229056079092429 83
UVM_INFO @ 2292000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
clkmgr_same_csr_outstanding 68010415659377935864132834038253414025553617860620483819234817602678714607677 81
UVM_INFO @ 7432329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---