Simulation Results: dma

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 83.42 %
  • code
  • 90.76 %
  • assert
  • 96.40 %
  • func
  • 63.09 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 1 1 100.00
dma_memory_smoke 6.000s 3955.714us 1 1 100.00
dma_handshake_smoke 1 1 100.00
dma_handshake_smoke 7.000s 1187.910us 1 1 100.00
dma_generic_smoke 1 1 100.00
dma_generic_smoke 6.000s 300.836us 1 1 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 33.816us 1 1 100.00
csr_rw 1 1 100.00
dma_csr_rw 2.000s 117.451us 1 1 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 14.000s 469.547us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 340.434us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
dma_csr_mem_rw_with_rand_reset 1.000s 80.833us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
dma_csr_rw 2.000s 117.451us 1 1 100.00
dma_csr_aliasing 3.000s 340.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 1 1 100.00
dma_memory_region_lock 120.000s 6798.308us 1 1 100.00
dma_memory_tl_error 1 1 100.00
dma_memory_stress 313.000s 159039.180us 1 1 100.00
dma_handshake_tl_error 1 1 100.00
dma_handshake_stress 885.000s 149075.231us 1 1 100.00
dma_handshake_stress 1 1 100.00
dma_handshake_stress 885.000s 149075.231us 1 1 100.00
dma_memory_stress 1 1 100.00
dma_memory_stress 313.000s 159039.180us 1 1 100.00
dma_generic_stress 1 1 100.00
dma_generic_stress 394.000s 49214.251us 1 1 100.00
dma_handshake_mem_buffer_overflow 1 1 100.00
dma_handshake_stress 885.000s 149075.231us 1 1 100.00
dma_abort 1 1 100.00
dma_abort 9.000s 589.724us 1 1 100.00
dma_stress_all 1 1 100.00
dma_stress_all 60.000s 30144.117us 1 1 100.00
alert_test 1 1 100.00
dma_alert_test 1.000s 12.379us 1 1 100.00
intr_test 1 1 100.00
dma_intr_test 1.000s 14.712us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
dma_tl_errors 3.000s 446.972us 1 1 100.00
tl_d_illegal_access 1 1 100.00
dma_tl_errors 3.000s 446.972us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
dma_csr_hw_reset 1.000s 33.816us 1 1 100.00
dma_csr_rw 2.000s 117.451us 1 1 100.00
dma_csr_aliasing 3.000s 340.434us 1 1 100.00
dma_same_csr_outstanding 2.000s 25.629us 1 1 100.00
tl_d_partial_access 4 4 100.00
dma_csr_hw_reset 1.000s 33.816us 1 1 100.00
dma_csr_rw 2.000s 117.451us 1 1 100.00
dma_csr_aliasing 3.000s 340.434us 1 1 100.00
dma_same_csr_outstanding 2.000s 25.629us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 3 3 100.00
dma_mem_enabled 15.000s 731.246us 1 1 100.00
dma_generic_stress 394.000s 49214.251us 1 1 100.00
dma_handshake_stress 885.000s 149075.231us 1 1 100.00
dma_config_lock 1 1 100.00
dma_config_lock 8.000s 339.717us 1 1 100.00
tl_intg_err 2 2 100.00
dma_tl_intg_err 3.000s 96.382us 1 1 100.00
dma_sec_cm 1.000s 39.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 3 66.67
dma_short_transfer 143.000s 12614.253us 1 1 100.00
dma_longer_transfer 6.000s 305.191us 1 1 100.00
dma_stress_all_with_rand_reset 73.000s 9220.871us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 86604890827493842688676632511363599267793576688180528036759889601492443493276 209
UVM_INFO @ 9220870886ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---