Simulation Results: entropy_src/rng_16bits

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.81 %
  • code
  • 82.94 %
  • assert
  • 74.06 %
  • func
  • 52.42 %
  • block
  • 94.16 %
  • line
  • 97.82 %
  • branch
  • 86.22 %
  • toggle
  • 52.92 %
  • FSM
  • 94.79 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 3.000s 79.410us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 39.981us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 54.269us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 25.000s 3170.132us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.172us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 12.539us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 54.269us 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.172us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 3.000s 79.410us 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
entropy_src_fw_ov 131.000s 13160.846us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 131.000s 13160.846us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 286.000s 13063.339us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
entropy_src_intr 23.000s 771.848us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
entropy_src_functional_alerts 8.000s 237.087us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 193.000s 13078.260us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 3.000s 123.900us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 7.000s 198.790us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 19.809us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 3.000s 92.837us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 4.000s 46.982us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 4.000s 46.982us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 39.981us 1 1 100.00
entropy_src_csr_rw 2.000s 54.269us 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.172us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 443.045us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 39.981us 1 1 100.00
entropy_src_csr_rw 2.000s 54.269us 1 1 100.00
entropy_src_csr_aliasing 2.000s 18.172us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 443.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 3.000s 63.041us 1 1 100.00
entropy_src_tl_intg_err 5.000s 154.488us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
entropy_src_cfg_regwen 3.000s 76.518us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
entropy_src_fw_ov 131.000s 13160.846us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 123.900us 1 1 100.00
entropy_src_sec_cm 3.000s 63.041us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 3.000s 123.900us 1 1 100.00
entropy_src_sec_cm 3.000s 63.041us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 425.000s 14015.727us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 123.900us 1 1 100.00
entropy_src_sec_cm 3.000s 63.041us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 3.000s 123.900us 1 1 100.00
entropy_src_sec_cm 3.000s 63.041us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 3.000s 123.900us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 8.000s 237.087us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 5.000s 154.488us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 396.000s 13092.640us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 35.000s 822.260us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1661) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 80714566819861838873892314048325780006719873755654027963517310583504928480761 778
UVM_INFO @ 822260431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 83101700394823530210972658942471935918202058136485924741301004786269127167607 113
UVM_INFO @ 12538503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---