Simulation Results: hmac

 
25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]
Coverage statistics
  • Total
  • 69.87 %
  • code
  • 83.15 %
  • assert
  • 97.17 %
  • func
  • 29.28 %
  • block
  • 97.42 %
  • line
  • 98.35 %
  • branch
  • 93.52 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.000s 256.449us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 97.207us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 2.000s 96.578us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 16.000s 1894.259us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 1.000s 34.726us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 3.000s 28.456us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 2.000s 96.578us 1 1 100.00
hmac_csr_aliasing 1.000s 34.726us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 53.000s 16590.015us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 86.000s 6568.471us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 242.000s 28466.579us 1 1 100.00
hmac_test_sha384_vectors 34.000s 331.447us 1 1 100.00
hmac_test_sha512_vectors 34.000s 1207.457us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 325.855us 1 1 100.00
hmac_test_hmac384_vectors 18.000s 912.793us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 348.528us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 15.000s 1047.462us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 457.000s 10423.101us 1 1 100.00
error 1 1 100.00
hmac_error 17.000s 934.839us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 21.000s 420.547us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.000s 256.449us 1 1 100.00
hmac_long_msg 53.000s 16590.015us 1 1 100.00
hmac_back_pressure 86.000s 6568.471us 1 1 100.00
hmac_datapath_stress 457.000s 10423.101us 1 1 100.00
hmac_burst_wr 15.000s 1047.462us 1 1 100.00
hmac_stress_all 163.000s 4205.036us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.000s 256.449us 1 1 100.00
hmac_long_msg 53.000s 16590.015us 1 1 100.00
hmac_back_pressure 86.000s 6568.471us 1 1 100.00
hmac_datapath_stress 457.000s 10423.101us 1 1 100.00
hmac_wipe_secret 21.000s 420.547us 1 1 100.00
hmac_test_sha256_vectors 242.000s 28466.579us 1 1 100.00
hmac_test_sha384_vectors 34.000s 331.447us 1 1 100.00
hmac_test_sha512_vectors 34.000s 1207.457us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 325.855us 1 1 100.00
hmac_test_hmac384_vectors 18.000s 912.793us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 348.528us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.000s 256.449us 1 1 100.00
hmac_long_msg 53.000s 16590.015us 1 1 100.00
hmac_back_pressure 86.000s 6568.471us 1 1 100.00
hmac_datapath_stress 457.000s 10423.101us 1 1 100.00
hmac_burst_wr 15.000s 1047.462us 1 1 100.00
hmac_error 17.000s 934.839us 1 1 100.00
hmac_wipe_secret 21.000s 420.547us 1 1 100.00
hmac_test_sha256_vectors 242.000s 28466.579us 1 1 100.00
hmac_test_sha384_vectors 34.000s 331.447us 1 1 100.00
hmac_test_sha512_vectors 34.000s 1207.457us 1 1 100.00
hmac_test_hmac256_vectors 15.000s 325.855us 1 1 100.00
hmac_test_hmac384_vectors 18.000s 912.793us 1 1 100.00
hmac_test_hmac512_vectors 16.000s 348.528us 1 1 100.00
hmac_stress_all 163.000s 4205.036us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 163.000s 4205.036us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 1.000s 47.424us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 1.000s 50.987us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 4.000s 243.487us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 4.000s 243.487us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 2.000s 97.207us 1 1 100.00
hmac_csr_rw 2.000s 96.578us 1 1 100.00
hmac_csr_aliasing 1.000s 34.726us 1 1 100.00
hmac_same_csr_outstanding 2.000s 118.681us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 2.000s 97.207us 1 1 100.00
hmac_csr_rw 2.000s 96.578us 1 1 100.00
hmac_csr_aliasing 1.000s 34.726us 1 1 100.00
hmac_same_csr_outstanding 2.000s 118.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 2.000s 103.951us 1 1 100.00
hmac_tl_intg_err 4.000s 188.310us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 4.000s 188.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.000s 256.449us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.000s 117.741us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 104.000s 5253.246us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 3450.973us 1 1 100.00