Simulation Results

Simulation Results: i2c

25/08/2026 21:46:36 DVSim: v1.52.0 sha: ca57617 json Branch: master Tool: xcelium [24.03-s007]

Coverage statistics

Total
88.05 %

code
85.64 %

assert
97.46 %

func
81.05 %

block
95.90 %

line
95.23 %

branch
92.63 %

toggle
72.68 %

FSM
82.01 %

Validation stages

V1		100.00%
V2		80.49%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	146.000s	7435.250us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	16.000s	5760.975us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.000s	55.260us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	2.000s	59.696us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	8.000s	1310.761us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	2.000s	86.415us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	2.000s	97.991us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	2.000s	59.696us	1	1	100.00
	i2c_csr_aliasing	2.000s	86.415us	1	1	100.00

33/41 passed

80.49 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	2.000s	21.571us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	27.000s	1191.820us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	1293.000s	5949.491us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	1.000s	24.063us	1	1	100.00
host_fifo_watermark				0	1	0.00
	i2c_host_fifo_watermark	3602.225s	0.000us	0	1	0.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	2615.000s	6914.305us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	3.000s	180.602us	1	1	100.00
	i2c_host_fifo_fmt_empty	5.000s	135.539us	1	1	100.00
	i2c_host_fifo_reset_rx	7.000s	603.986us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	925.000s	3744.408us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.000s	2450.895us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.000s	104.956us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	5.000s	1072.579us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	39.000s	10558.293us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	10.000s	3946.971us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	45.000s	1320.256us	1	1	100.00
	i2c_target_intr_smoke	5.000s	644.124us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	2.000s	371.964us	1	1	100.00
	i2c_target_fifo_reset_tx	3.000s	187.518us	1	1	100.00
target_fifo_full				1	3	33.33
	i2c_target_stress_wr	3600.000s	0.000us	0	1	0.00
	i2c_target_stress_rd	45.000s	1320.256us	1	1	100.00
	i2c_target_intr_stress_wr	3601.000s	0.000us	0	1	0.00
target_timeout				1	1	100.00
	i2c_target_timeout	10.000s	5662.027us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	18.000s	2396.233us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	9.000s	6257.237us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	12.000s	10571.813us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	4.000s	305.595us	1	1	100.00
	i2c_target_fifo_watermarks_tx	3.000s	3493.988us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	1293.000s	5949.491us	1	1	100.00
	i2c_host_perf_precise	3.000s	94.875us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.000s	2450.895us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.000s	57.674us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	5.000s	5464.816us	1	1	100.00
	i2c_target_nack_acqfull_addr	4.000s	1122.066us	1	1	100.00
	i2c_target_nack_txstretch	4.000s	173.329us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.000s	467.654us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	5.000s	471.904us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	1.000s	35.651us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.000s	17.826us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	3.000s	1656.136us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	3.000s	1656.136us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	55.260us	1	1	100.00
	i2c_csr_rw	2.000s	59.696us	1	1	100.00
	i2c_csr_aliasing	2.000s	86.415us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	165.258us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.000s	55.260us	1	1	100.00
	i2c_csr_rw	2.000s	59.696us	1	1	100.00
	i2c_csr_aliasing	2.000s	86.415us	1	1	100.00
	i2c_same_csr_outstanding	2.000s	165.258us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.000s	90.355us	1	1	100.00
	i2c_sec_cm	2.000s	98.525us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.000s	90.355us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	5.000s	179.798us	1
target_error_intr				1
	i2c_target_unexp_stop	3.000s	186.258us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	17.000s	978.250us	1

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				3 test runs
	i2c_host_fifo_watermark	63031182174809237056870287584896601830544243439968167934175287998635616366915	None
	i2c_target_stress_wr	103269723947443734152702102436605241652163869804832423201736654695673585160009	None
	i2c_target_intr_stress_wr	72608916999382176315568014093737738467455138103432742995311940955147264540018	None
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	68776264355148248288766675233948850442422507111545323477145904773117860027395	89	UVM_INFO @ 21570789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	68472299509175595774766474131246192039419393248270606233375940894297705836898	136	UVM_INFO @ 1191820098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	109681692415240802256751157811127728351229734566230843320244677066937166816380	90	UVM_INFO @ 104955558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	3741918974241893861793623285624464218511802164953828296183089161482837033291	113	UVM_INFO @ 179798495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	55689478893257902834204599652496968031968159434764222077525333064381152896185	98	UVM_INFO @ 978249995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	85980185420003113865985835015402056611900152782593271890387643506722080396113	93	UVM_INFO @ 1072579047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:680) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	57411598162890499414558096348064269434513001439190862337805582396047159332171	87	UVM_INFO @ 186258002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	11576261868086944541900064844842176779833543698185530959740526333069739452449	88	UVM_INFO @ 10571812648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---